90E21 Datasheet, PDF (16/57 Pages) Integrated Device Technology – Single-Phase High-Performance Wide-Span Energy Metering IC

90E21/22/23/24
SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
4
INTERFACE
4.1 SERIAL PERIPHERAL INTERFACE (SPI)
SPI is a full-duplex, synchronous channel. There are two SPI modes:
four-wire mode and three-wire mode. In four-wire mode, four pins are
used: CS, SCLK, SDI and SDO. In three-wire mode, three pins are
used: SCLK, SDI and SDO. Data on SDI is shifted into the chip on the
rising edge of SCLK while data on SDO is shifted out of the chip on the
falling edge of SCLK. The LastSPIData register (06H) stores the 16-bit
data that is just read or written.
4.1.1 FOUR-WIRE MODE
In four-wire mode, the CS pin must be driven low for the entire read
or write operation. The first bit on SDI defines the access type and the
lower 7-bit is decoded as address.
Read Sequence
As shown in Figure-6, a read operation is initiated by a high on SDI
followed by a 7-bit register address. A 16-bit data in this register is then
shifted out of the chip on SDO. A complete read operation contains 24
cycles.
CS
SCLK
SDI
SDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Register Address
A6 A5 A4 A3 A2 A1 A0
Don't care
High Impedance
16-bit data
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure-6 Read Sequence in Four-Wire Mode
Write Sequence
As shown in Figure-7, a write operation is initiated by a low on SDI
followed by a 7-bit register address. A 16-bit data is then shifted into the
chip on SDI. A complete write operation contains 24 cycles.
CS
SCLK
SDI
SDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Register Address
16-bit data
A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
High Impedance
Figure-7 Write Sequence in Four-Wire Mode
Interface
16
January 10, 2012