MC88LV926 Datasheet, PDF (5/11 Pages) Motorola, Inc – LOW SKEW CMOS PLL 68060 CLOCK DRIVER

MC88LV926
Low Skew CMOS PLL 68060 Clock Driver
NETCOM
Table 6. Frequency Specifications (T_A = 0°C to 70°C; V_CC = 3.3 V ± 0.3 V
Symbol
Parameter
Guaranteed Minimum
Fmax (2X_Q) Maximum Operating Frequency, 2X_Q Output
66
Fmax (‘Q')
Maximum Operating Frequency,
33
Q0–Q3 Outputs
NOTE: Maximum Operating Frequency is guaranteed with the 88LV926 in a phase-locked condition.
Unit
MHz
MHz
Table 7. AC Characteristics (T_A = 0°C to 70°C; V_CC = 3.3V ± 0.3V
Symbol
Parameter
Minimum
t_RISE/FALL
Rise/Fall Time, into 50Ω Load
0.3
All Outputs
t_RISE/FALL
Rise/Fall Time into a 50Ω Load
0.5
2X_Q Output
t_pulse
(1)
width(a)
(Q0, Q1, Q2, Q3)
t_pulse
(1)
width(b)
(2X_Q Output)
t_SKEWr(2)
(Rising)
Output Pulse Width
Q0, Q1, Q2, Q3 at 1.65V
Output Pulse Width
2X_Q at 1.65V
Output–to–Output Skew
Between Outputs Q0–Q2
(Rising Edge Only)
0.5t_cycle – 0.5
0.5t_cycle – 0.5
–
t_SKEWf(2)
Output–to–Output Skew
–
(Falling)
Between Outputs Q0–Q2
(Falling Edge Only)
t_SKEWall(2)
Output–to–Output Skew
–
2X_Q, Q0–Q2, Q3
t_SKEW QCLKEN^{(1) Output–to–Output Skew}
(2)
QCLKEN to 2X_Q 2X_Q = 50 MHz
2X_Q = 66 MHz
t_LOCK(4)
t_PHL MR – Q⁽¹⁾
Phase–Lock Acquisition Time,
All Outputs to SYNC Input
Propagation Delay,
MR to Any Output (High–Low)
t_REC, MR to
SYNC⁽¹⁾⁽⁵⁾
Reset Recovery Time rising MR edge to
falling SYNC edge⁽⁶⁾
t_W, MR LOW^{(1) (5) Minimum Pulse Width, MR input Low}
t_W, RST_IN
LOW⁽¹⁾
Minimum Pulse Width, RST_IN Low
t_PZL(1)
Output Enable Time
RST_IN Low to RST_OUT Low
t_PLZ(1)
Output Enable Time
RST_IN High to RST_OUT High Z
9.7⁽³⁾
7.0⁽³⁾
1
1.5
9
5
10
1.5
1016 ‘Q' Cycles
(508 Q/2 Cycles)
Maximum
1.6
1.6
0.5t_cycle + 0.5
0.5t_cycle + 0.5
500
1.0
750
–
Unit
Condition
ns ^tRISE ^{– 0.8 V to 2.0 V}
t_FALL – 2.0 V to 0.8 V
ns ^tRISE ^{– 0.8 V to 2.0 V}
t_FALL – 2.0 V to 0.8 V
ns ^{50 Ω Load Terminated to V}CC^/
2 (See Application Note 3)
ns ^{50 Ω Load Terminated to V}CC^/
2 (See Application Note 3)
ps ^{Into a 50Ω Load Terminated to}
V_CC/2 (See Timing Diagram in
Figure 6)
ns ^{Into a 50 Ω Load Terminated to}
V_CC/2 (See Timing Diagram in
Figure 6)
ps ^{Into a 50 Ω Load Terminated to}
V_CC/2 (See Timing Diagram in
Figure 6)
ns ^{Into a 50 Ω Load Terminated to}
V_CC/2 (See Timing Diagram in
Figure 6)
10
ms
13.5
ns ^{Into a 50 Ω Load}
Terminated to V_CC/2
–
ns
–
ns
–
ns ^{When in Phase–Lock}
16.5
1024 ‘Q' Cycles
(512 Q/2 Cycles)
ns ^{See Application Notes, Note 5}
ns ^{See Application Notes, Note 5}
1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this
methodology.
2. Under equally loaded conditions and at a fixed temperature and voltage.
3. Guaranteed that QCLKEN will meet the setup and hold time requirement of the 68060.
4. With V_CC fully powered–on: t_CLOCK Max is with C1 = 0.1 μF; t_LOCK Min is with C1 = 0.01 μF.
5. Specification is valid only when the PLL_EN pin is low.
6. See Application Notes, Note 4 for the distribution in time of each output referenced to SYNC.
IDT™ Low Skew CMOS PLL 68060 Clock Driver
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Freescale Semiconductor
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MC88LV_M92_C6_88LV926
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