MC88LV926 Datasheet, PDF (2/11 Pages) Motorola, Inc – LOW SKEW CMOS PLL 68060 CLOCK DRIVER

MC88LV926
Low Skew CMOS PLL 68060 Clock Driver
NETCOM
Q3 ¹
V_CC 2
MR 3
RST_IN ⁴
V_CC(AN) 5
RC1 6
GND(AN) 7
SYNC 8
GND 9
Q0 10
20 GND
19 2X_Q
18 QCLKEN
17 V_CC
16 Q2
15 GND
14 RST_OUT(LOCK)
13 PLL_EN
12 Q1
11 V_CC
Figure 1. Pinout: 20-Lead Wide SOIC Package (Top View)
Description of the RST_IN/RST_OUT(LOCK)
Functionality (continued)
After the system start-up is complete and the 88LV926 is
phase-locked to the SYNC input signal (RST_OUT high), the
processor reset functionality can be utilized. When the
RST_IN pin is toggled low (min. pulse width=10 nS),
RST_OUT(LOCK) will go to the low state and remain there
for 1024 cycles of the ‘Q' output frequency (512 SYNC
cycles). During the time in which the RST_OUT(LOCK) is
actively pulled low, all the 88LV926 clock outputs will continue
operating correctly and in a locked condition to the SYNC
input (clock signals to the 68030/040/060 family of
processors must continue while the processor is in reset). A
propagation delay after the 1024th cycle RST_OUT(LOCK)
goes back to the high impedance state to be pulled high by
the resistor.
Power Supply Ramp Rate Restriction for Correct 030/040
Processor Reset Operation During System Start-up
Because the RST_OUT(LOCK) pin is an indicator of
phase-lock to the reference source, some constraints must
be placed on the power supply ramp rate to make sure the
RST_OUT(LOCK) signal holds the processor in reset during
system start-up (power-up). With the recommended loop filter
values (see Figure 7) the lock time is approximately 10ms.
The phase-lock loop will begin attempting to lock to a
reference source (if it is present) when V_CC reaches 2 V. If the
V_CC ramp rate is significantly slower than 10 ms, then the
PLL could lock to the reference source, causing
RST_OUT(LOCK) to go high before the 88LV926 and 030/
040 processor is fully powered up, violating the processor
reset specification. Therefore, if it is necessary for the
RST_IN pin to be held high during power-up, the V_CC ramp
rate must be less than 10 mS for proper 68030/040/060 reset
operation.
This ramp rate restriction can be ignored if the RST_IN pin
can be held low during system start-up (which holds
RST_OUT low). The RST_OUT(LOCK) pin will then be pulled
back high 1024 cycles after the RST_IN pin goes high.
Table 1. Capacitance and Power Specifications
Symbol
C_IN
Parameter
Input Capacitance
C_PD
Power Dissipation Capacitance
PD₁
Power Dissipation at 33MHz With 50Ω
Thevenin Termination
PD₂
Power Dissipation at 33MHz With 50Ω
Parallel Termination to GND
Value Type
4.5⁽¹⁾
40⁽¹⁾
15mW/Output⁽¹⁾
90mW/Device
37.5mW/Output⁽¹⁾
225mW/Device
Unit
pF
pF
mW
mW
Test Conditions
V_CC = 3.3 V
V_CC = 3.3 V
V_CC = 3.3 V
T = 25°C
V_CC = 3.3 V
T = 25°C
1. Value at V_CC = 3.3 V TBD
IDT™ Lo^Mw ^CS⁸ke⁸w^LVC⁹M²O⁶S PLL 68060 Clock Driver
MC88LV926
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