ICSSSTUAF32868A Datasheet, PDF (5/22 Pages) Integrated Device Technology – 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Parity Logic Diagram
M2
RESET
CLK ^L1
CLK ^M1
D1-D12,
D17-D20,
D22,
D24-D28
22
VREF ^{A5, AB5}
PAR_IN L3
DCS0 ^N1
CSGEN ^L2
DCS1
P1
D1-D12,
D17-D20, D22,
D24-D28
22
D
CK Q
R
CE
D
CK Q
R
CE
D1-D12,
D17-D20, D22,
D24-D28
22
22 ^D1-D12,
D17-D20, D22,
D24-D28
Parity Generator
and
Error Check
D
CK Q
R
Q1A-Q12A,
22 Q17A-Q20A,
Q22A,
Q24A-Q28A
Q1B-Q12B,
22 _Q17B-Q20B,
Q22B,
Q24B-Q28B
M3 _QERR
N2 _QCS0A
M7 _QCS0B
D
CK Q
R
P2 _QCS1A
M8 _QCS1B
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
5
ICSSSTUAF32868A
7094/14