ICSSSTUAF32868A Datasheet, PDF (11/22 Pages) Integrated Device Technology – 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Terminal Functions
Terminal Name
GND
VDD
VREF
CLK
CLK
C
RESET
CSGEN
D1 - D28
DCS0, DCS1
DCKE0, DCKE1
DODT0, DODT1
PAR_IN
Q1 - Q28
QCS0, QCS1
QCKE0, QCKE1
QODT0, QODT1
QERR
NC
Electrical
Characteristics
Ground Input
1.8V nominal
0.9V nominal
Differential Input
Differential Input
LVCMOS Input
LVCMOS Input
LVCMOS Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
1.8V CMOS
1.8V CMOS
1.8V CMOS
1.8V CMOS
Open Drain Output
Description
Ground
Power Supply Voltage
Input Reference Clock
Positive Master Clock Input
Negative Master Clock Input
Configuration Control Inputs - Register A or Register B
Asynchronous Reset Input. Resets registers and disables Vref data
and clock differential-input receivers.
Chip select gate enable – When high, D1-D28 inputs will be latched
only when at least one chip select input is low during the rising edge
of the clock. When low, the D1-D28 inputs will be latched and
redriven on every rising edge of the clock.
Data Input. Clocked in on the crossing of the rising edge of CLK
and the falling edge of CLK.
Chip select inputs – These pins initiate DRAM address/command
decodes, and as such at least one will be low when a valid
address/command is present. The Register can be programmed to
redrive all D inputs (CSGEN high) only when at least one chip select
input is low. If CSGEN, DCS0, and DCS1 inputs are high, D1-D28
inputs will be disabled.
The outputs of this register bit will not be suspended by the DCS0
and DCS1 controls
The outputs of this register bit will not be suspended by the DCS0
and DCS1 controls
Parity Input arrives one cycle after corresponding data input
Data Outputs that are suspended by the DCS0 and DCS1 controls
Data Output that will not be suspended by the DCS0 and DCS1
controls
Data Output that will not be suspended by the DCS0 and DCS1
controls
Data Output that will not be suspended by the DCS0 and DCS1
controls
Output Error bit, generated one cycle after the corresponding data
output
No Connection
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
11
ICSSSTUAF32868A
7094/14