ICSSSTUAF32868A Datasheet, PDF (14/22 Pages) Integrated Device Technology – 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
VDD = 1.8V ± 0.1V
Symbol Parameter
Min. Max. Units
fCLOCK Clock Frequency
410
MHz
tW
tACT1,2
tINACT1,3
Pulse Duration, CLK, CLK HIGH or LOW
Differential Inputs Active Time
Differential Inputs Inactive Time
1
ns
10
ns
15
ns
DCS0 before CLK↑, CLK↓, DCS1 and CSGEN HIGH; 0.7
ns
DCS1 before CLK↑, CLK↓, DCS0 and CSGEN HIGH;
tSU
Setup
Time
DCS0 before CLK↑, CLK↓, DCS1 LOW and CSGEN
HIGH or LOW; DCS1 before CLK↑, CLK↓, DCS0
LOW and CSGEN HIGH or LOW
0.5
ns
DODTn, DCKEn, PAR_IN, and data before CLK↑,
0.5
ns
CLK↓
tH
Hold ^{DCSn, DODT,n DCKEn, and data after CLK↑, CLK↓}
0.5
Time _{PAR_IN after CLK↑, CLK↓}
0.5
ns
ns
1 This parameter is not production tested.
2 VREF must be held at a valid input voltage level and data inputs must be held at valid voltage levels for
a minimum time of tACT (max) after RESET is taken HIGH.
3 VREF data and clock inputs must be held at valid input voltage levels (not floating) for a minimum time
of tINACT (max) after RESET is taken LOW.
Switching Characteristics Over Recommended Free Air Operating Range
(unless otherwise noted)
Symbol
fMAX
tPDM
tPDMSS
tLH
tHL
tPLH
tPHL
Parameter
Max Input Clock Frequency
Propagation Delay, single bit switching, CLK↑ to CLK↓ to Qn
Propagation Delay, simultaneous switching, CLK↑ to CLK↓ to Qn
LOW to HIGH Propagation Delay, CLK↑ to CLK↓ to QERR
HIGH to LOW Propagation Delay, CLK↑ to CLK↓ to QERR
HIGH to LOW Propagation Delay, RESET↓ to Qn↓
LOW to HIGH Propagation Delay, RESET↓ to QERR↑
VDD = 1.8V ± 0.1V
Min.
Max.
410
1.3
1.9
2
1.2
3
1
2.4
3
3
Units
MHz
ns
ns
ns
ns
ns
ns
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
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ICSSSTUAF32868A
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