ICS9LPRS525_1107 Datasheet, PDF (5/21 Pages) Integrated Device Technology – 56-pin CK505 for Intel Systems

ICS9LPRS525
PC MAIN CLOCK
Absolute Maximum Ratings - DC Parameters
PARAMETER
SYMBOL
CONDITIONS
Maximum Supply Voltage
VDDxxx
Supply Voltage
Maximum Supply Voltage
VDDxxx_IO
Low-Voltage Differential I/O Supply
Maximum Input Voltage
V_IH
Minimum Input Voltage
V_IL
Storage Temperature
Ts
3.3V Inputs
Any Input
-
Case Temperature
Tc
Input ESD protection
ESD prot
Human Body Model
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Operation under these conditions is neither implied, nor guaranteed.}
3 _{Maximum input voltage is not to exceed VDD}
MIN
GND - 0.5
-65
2000
MAX
4.6
3.8
4.6
150
115
UNITS
V
V
V
V
°_C
°_C
V
Notes
7
7
4,5,7
4,7
4,7
4,7
6,7
Electrical Characteristics - Input/Supply/Common Output DC Parameters
PARAMETER
Ambient Operating Temp
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Low Threshold Input- High Voltage
SYMBOL
Tam bie nt
VDDxxx
VDDxxx_IO
V _{IHS E}
VIL SE
V_{IH _FS_ TEST}
CONDITIONS
-
Supply Voltage
Low-Voltage Differential I/O Supply
Single-ended 3.3V inputs
Single-ended 3.3V inputs
3.3 V +/-5%
L ow Threshold Input- FSC = '1' Voltage VIH_FS_ FSC
3.3 V +/-5%
Low Threshold Input- FSA,FSB = '1'
Vo ltag e
Low Threshold Input-Low Voltage
PCI3/CFG0 Input
PCI3/CFG0 Input
PCI3/CFG0 Input
Input Leakage Current
Input Leakage Current
Output High Voltage
Output Low Voltage
Operating Supply Current
iAMT Mode Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
Clk Stabilization
Td riv e_CR_ off
Td riv e_CR_ on
Tdriv e_ CPU
Tfall_SE
Trise_SE
SMBus Voltage
Low-level Output Voltage
Current sinking at VOL SMB = 0.4 V
SCL K/S DATA
Clock/Data Rise Time
SCL K/S DATA
Clock/Data Fall Time
VIH_F S_F SAB
VIL _FS
V_{I L_CF GHI}
V_{IL _CF GMID}
VIL_ CF GLO
I_IN
IINR ES
V _{O HS E}
V_{O LS E}
ID DOP3.3
I_{D DOPIO}
IDD iAM T3.3
I_{D DiAMTIO}
I_{D DPD 3.3}
IDDPD IO
F_i
L pin
C_IN
C_{O UT}
CIN X
T_STAB
T_{DR CROFF}
TDRC RON
T_{DR SRC}
T_{F ALL}
TR ISE
V_DD
V_{OLSM B}
IPULLU P
T_RI2C
T_{F I2C}
3.3 V +/-5%
3.3 V +/-5%
Optional input, 2.75V typ.
Optional input, 1.65V typ.
Optional input, 0.55V typ.
V_IN = V_{DD ,} V_IN = GND
Inputs with pull up or pull down resistors
V_IN = V_{DD ,} V_IN = GND
Single-ended outputs, I_OH = -1mA
Single-ended outputs, I_OL = 1 mA
Full Active, CL = Full load; Idd 3.3V
Full Active, C_L = Full load; IDD IO
M1 mode, 3.3V Rail
M1 Mode, IO Rail
Power down mode, 3.3V Rail
Power down mode, IO Rail
V_DD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or de-assertion of PD to 1st
clock
Output stop after CR deasserted
Output run after CR asserted
CPU output enable after
PCI_STOP# de-assertion
Fall/rise time of all 3.3V control inputs from 20-80%
@ I_{PU LLU P}
SMB D ata Pin
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
Maximum SMBus Operating Frequency
F_{SMBU S}
Spread Spectrum Modulation Frequency fSSM OD
Triangular Modulation
MIN
0
3.1 35
0.99 75
2
VSS - 0.3
2
MAX U NITS
70
°C
3.465
V
3.465
V
V_{D D} + 0.3
V
0.8
V
VDD + 0.3 V
Notes
10
3
3
8
0. 7
1.5
V
8
0. 7
VSS - 0.3
2. 4
1. 3
VSS - 0.3
-5
-2 00
2. 4
1. 5
2. 7
4
VDD+0.3
0.35
VDD+0.3
2
0.9
5
2 00
0.4
1 50
70
40
12
6
0.7
15
7
5
6
6
1.8
4 00
0
10
10
10
5.5
0.4
10 00
V
V
V
V
V
uA
uA
V
V
mA
mA
mA
mA
mA
mA
MHz
nH
pF
pF
pF
ms
ns
us
ns
ns
ns
V
V
mA
ns
9, 10
9, 10
9, 10
2
1
1
10
10
3 00
ns
1 00
kHz
30
33
kHz
IDT^TM PC MAIN CLOCK
1484E—07/07/11
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