ICS9LPRS525_1107 Datasheet, PDF (17/21 Pages) Integrated Device Technology – 56-pin CK505 for Intel Systems

ICS9LPRS525
PC MAIN CLOCK
Byte 12 Byte Count Register
Bit Pin
Name
7
Reserved
6
Reserved
5
BC5
4
BC4
3
BC3
2
BC2
1
BC1
0
BC0
Byte 13 to 28 Reserved
Byte 29 Slew Rate Control
Bit Pin
Name
7
USB_Slew1
6
USB_Slew0
5
PCI_Slew1
4
PCI_Slew0
3
Reserved
2
REF Slew Rate
1
Reserved
0
Reserved
Description
Read Back byte count register,
max bytes = 32
Description
USB Slew Rate Control (MSB)
USB Slew Rate Control (LSB)
PCI Slew Rate Control (MSB)
PCI Slew Rate Control (LSB)
Changes Ref Slew Rate
Type
0
RW
RW
RW
RW
RW
RW
RW
RW
1
Default
0
0
0
0
1
1
0
1
RW
0
1
Default
RW _{See Slew Rate Selection Table}
1
RW
0
RW _{See Slew Rate Selection Table}
1
RW
1
RW
1
RW
1.2V/ns
2.2V/ns
1
RW
0
RW
0
IDT^TM PC MAIN CLOCK
17
1484E—07/07/11