ICS9LPRS525_1107 Datasheet, PDF (11/21 Pages) Integrated Device Technology – 56-pin CK505 for Intel Systems

ICS9LPRS525
PC MAIN CLOCK
Table 3: IO_Vout select table
B9b2 B9b1 B9b0 IO_Vout
0
0
0
0.3V
0
0
1
0.4V
0
1
0
0.5V
0
1
1
0.6V
1
0
0
0.7V
1
0
1
0.8V
1
1
0
0.9V
1
1
1
1.0V
Table 4: Device ID table
B8b7 B8b6 B8b5 B8b4
Comment
0
0
0
0
56 pin TSSOP
Table 5: Slew Rate Selection Table
Bit 1 Bit 0
Slew Rate
0
0
HI-Z
0
1
0.7X (1.4V/ns)
1
0
0.8X (1.6 V/ns)
1
1
1X (2.0 V/ns)
Table 6. PCI3 Configuration Table
Note: 2 bits are needed since
CFG0 is tri-level input
SRC_Main_SE
PCI3/CFG0 PCI2/TME PCI3_CFG1 PCI3_CFG0
L
HW Strap HW Strap (Byte 11, bit 7) (Byte 11, bit 6) (Byte 0, bit 2) Config Mode
Low
0 or 1
0
0
0
0 = Default
Mid
0 or 1
0
1
1
1
High
TME=0
1
0
1
2
High
TME=1
1
1
1
3
Table 7. PLL Modes for PCI3 Configurations
Config
PLL1
PLL2
Mode
Outputs
SSC
Outputs
SSC
CPU/SRC/
0 = Default
PCI
Down
USB
NA
1
CPU
Down
USB
NA
2
CPU
Center
USB
NA
3
CPU
Center
USB/LAN25
NA
*Note: In Mode 3, Byte 8, bit (1:0) must be set to '1' to enable pin 17,18
PLL3
Outputs
SSC
-
SRC/PCI
SRC/PCI
SRC/PCI
-
Down
Down
Down
SRC1
PLL Source
PLL1
(Table 2
100MHz applies)
100MHz
PLL3
100MHz
PLL3
25MHz SE PLL2*
Table 8. ME Clock Selection Table
PCIF5/
ITP_EN iAMT_EN CPU2_AMT_EN CPU1_AMT_EN
Description
x
1
0
0
Reserved
x
1
0
1
Default, CPU1 = iAMT Clock
1
1
1
0
CPU2 = iAMT Clock
1
1
1
1
CPU1 and CPU2 both run in iAMT mode
IDT^TM PC MAIN CLOCK
1484E—07/07/11
11