ICS9FG1201H Datasheet, PDF (5/21 Pages) Integrated Device Technology – Frequency Generator for CPU, PCIe Gen1 & Fully Buffered DIMM Clocks

ICS9FG1201H
Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201 Programmable Gear Ratios
SMBus
Byte 0
Input Output Gear Ratio
(m) (n)
(n/m)
Input (CPU FSB) and Output
Frequencies (MHz)
200.0 266.7 320.0 333.3 400.0
00000 3
1
00001 5
2
0 0 0 1 0 12
5
00011 2
1
00100 5
3
00101 8
5
00110 3
2
0.333
0.400
0.417
0.500
0.600
0.625
0.667
66.7
80.0
83.3
100.0
120.0
125.0
133.3
88.9
106.7
111.1
133.3
160.0
166.7
177.8
106.7
128.0
133.3
160.0
192.0
200.0
213.3
111.1
133.3
138.9
166.7
200.0
208.3
222.2
133.3
160.0
166.7
200.0
240.0
250.0
266.7
00111 4
3
0.750 150.0 200.0 240.0 250.0 300.0
01000 6
5
01001 1
1
01010 5
6
01011 4
5
01100 3
4
01101 2
3
01110 3
5
01111 1
2
0.833
1.000
1.200
1.250
1.333
1.500
1.667
2.000
166.7
200.0
240.0
250.0
266.7
300.0
333.3
400.0
222.2
266.7
320.0
333.3
355.6
400.0
NA
NA
266.7
320.0
384.0
400.0
NA
NA
NA
NA
277.8
333.3
400.0
NA
NA
NA
NA
NA
333.3
400.0
NA
NA
NA
NA
NA
NA
CLK IN (CPU FSB) Frequency (MHz)
100 133.33 160 166.67
10000 3
1
10001 5
2
1 0 0 1 0 12
5
10011 2
1
0.333
0.400
NA 53.3 64.0 66.7
0.417
NA 55.6 66.7 69.4
0.500 50.0 66.7 80.0 83.3
10100 5
3
10101 8
5
10110 3
2
0.600
0.625
0.667
60.0 80.0
62.5 83.3
66.7 88.9
96.0
100.0
106.7
100.0
104.2
111.1
10111 5
4
0.800 80.0 106.7 128.0 133.3
11000 6
5
0.833
NA 111.1 133.3 138.9
11001 1
1
11010 5
6
11011 4
5
1.000
1.200
1.250
100.0 133.3
120.0 160.0
125.0 166.7
160.0
192.0
200.0
166.7
200.0
208.3
11100 3
4
11101 2
3
11110 3
5
11111 1
2
1.333
1.500
1.667
2.000
133.3
150.0
166.7
200.0
177.8
200.0
222.2
266.7
213.3
266.7
320.0
222.2
277.8
333.3
Note: Lines in BOLD are Power-up defaults for FS_A_410 = 0 and 1 respectively.
Shaded areas are shown for reference only and are not necessarily valid operating points
IDT^TM/ICS^TM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
5
ICS9FG1201H 10/22/07