ICS9FG1201H Datasheet, PDF (1/21 Pages) Integrated Device Technology – Frequency Generator for CPU, PCIe Gen1 & Fully Buffered DIMM Clocks

DATASHEET
Frequency Generator for CPU, PCIe Gen1* & Fully Buffered
DIMM Clocks
ICS9FG1201H
Description
Features/Benefits
ICS9FG1201 follows the Intel DB1200G Differential Buffer •
Specification. This buffer provides 12 output clocks for CPU Host
Bus, PCI Express, or Fully Buffered DIMM applications. The outputs
•
are configured with two groups. Both groups (DIF 9:0) and (DIF
11:10) can be equal to or have a gear ratio to the input clock. A ^•
differential CPU clock from a CK410 or CK410B main clock generator,
such as the ICS954101 or ICS932S401, drives the ICS9FG1201. _•
ICS9FG1201 can provide outputs up to 400MHz.
•
Power up default is all outputs in 1:1 mode
DIF_(9:0) can be “gear-shifted” from the input CPU Host
Clock
DIF_(11:10) can be “gear-shifted” from the input CPU Host
Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
• 8 Selectable SMBus addresses
• SMBus address determines PLL or Bypass mode
Key Specifications
• DIF output cycle-to-cycle jitter < 50ps
• DIF output-to-output skew < 50ps within a group
• DIF output-to-output skew < 100ns across all outputs
• 56-pin SSOP/TSSOP package
• Available in RoHS compliant packaging
Funtional Block Diagram
OE#
10
OE(9:0)#
SPREAD
COMPATIBLE
PLL
CLK_IN
CLK_IN#
SPREAD
COMPATIBLE
PLL
HIGH_BW#
FS_A_410
VTT_PWRGD#/PD
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
CONTROL
LOGIC
GEAR
SHIFT
STOP
2
LOGIC
LOGIC
DIF(11:10)
GEAR
SHIFT
LOGIC
STOP
10
LOGIC
DIF(9:0)
IREF
IDT^TM/ICS^TM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
1
ICS9FG1201H 10/22/07