ICS9FG1201H Datasheet, PDF (16/21 Pages) Integrated Device Technology – Frequency Generator for CPU, PCIe Gen1 & Fully Buffered DIMM Clocks

ICS9FG1201H
Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
Electrical Characteristics - Skew and Differential Jitter Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
Group
Parameter
Description
CLK_IN, DIF[x:0] t_{SPO_PLL}
Input-to-Output Skew in PLL mode (1:1 only),
nominal value @ 25°C, 3.3V
CLK_IN, DIF[x:0] t_{PD_BYP}
Input-to-Output Skew in Bypass mode (1:1 only),
nominal value @ 25°C, 3.3V
DIF[11:10]
t_{SKEW_G2}
Output-to-Output Skew Group of 2
(Common to Bypass and PLL mode)
DIF[9:0]
t_{SKEW_G10}
Output-to-Output Skew Group of 10
(Common to Bypass and PLL mode)
DIF[11:0]
t_{SKEW_A12}
Output-to-Output Skew across all 12 outputs (Common to
Bypass and PLL mode - all outputs at same gear)
Min Typ Max Units Notes
-500
500 ps ^1,2,4,5,6,
10
2.5
4.5 ns ^1,2,3,5,
10
50 ps 1,2,10
50 ps 1,2,10
100 ps 1,2,3,10
PLL Jitter Peaking j_peak-hibw
(HIGH_BW# = 0)
0
2.5 dB
9,10
PLL Jitter Peaking j_peak-lobw
(HIGH_BW# = 1)
0
2
dB
9,10
PLL Bandwidth
pll_HIBW
(HIGH_BW# = 0)
2
4
PLL Bandwidth
pll_LOBW
(HIGH_BW# = 1)
0.7
1.4
PCIe Gen 1 phase jitter
108
Jitter, Phase
t_jphasePLL
(1.5 - 22 MHz)
FBD phase jitter
3
(11-33 MHz)
NOTES:
1. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2. Measured from differential cross-point to differential cross-point
3. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4. This parameter is deterministic for a given device
5. Measured with scope averaging on to find mean value.
6. t is the period of the input clock
7. See http://www.pcisig.com for complete specs
8. Device driven by 932S401EGLF or equivalent
9. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.
10. Guaranteed by design and characterization, not 100% tested in production.
11. Measured at 3 db dow n or half pow er point.
MHz
MHz
10,11
10,11
ps 1,7,8,10
ps rms 1,7,8,10
IDT^TM/ICS^TM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
16
ICS9FG1201H 10/22/07