ICS9DB803DI Datasheet, PDF (5/21 Pages) Integrated Device Technology – Eight Output Differential Buffer for PCIe Gen 2

ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
Pin Description for OE_INV = 1
PIN # PIN NAME
PIN TYPE
1 SRC_DIV#
IN
DESCRIPTION
Active low Input for determining SRC output frequency SRC or SRC/2.
0 = SRC/2, 1= SRC
2 VDD
PWR
Power supply, nominal 3.3V
3 GND
4 SRC_IN
5 SRC_IN#
6 OE0#
7 OE3#
8 DIF_0
9 DIF_0#
10 GND
11 VDD
PWR
IN
IN
IN
IN
OUT
OUT
PWR
PWR
Ground pin.
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Ground pin.
Power supply, nominal 3.3V
12 DIF_1
13 DIF_1#
14 OE1#
15 OE2#
16 DIF_2
17 DIF_2#
18 GND
19 VDD
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Ground pin.
Power supply, nominal 3.3V
20 DIF_3
OUT
0.7V differential true clock output
21 DIF_3#
OUT
0.7V differential complement clock output
22 BYPASS#/PLL
23 SCLK
24 SDATA
IN
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
IN
Clock pin of SMBus circuitry, 5V tolerant.
I/O
Data pin for SMBus circuitry, 5V tolerant.
IDT^TM/ICS^TM Eight Output Differential Buffer for PCIe Gen 2
5
ICS9DB803DI REV A 06/18/08