ICS9DB803DI Datasheet, PDF (3/21 Pages) Integrated Device Technology – Eight Output Differential Buffer for PCIe Gen 2

ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
Pin Description for OE_INV = 0
PIN # PIN NAME PIN TYPE
DESCRIPTION
1 SRC_DIV#
IN
Active low Input for determining SRC output frequency SRC or SRC/2.
0 = SRC/2, 1= SRC
2 VDD
3 GND
4 SRC_IN
5 SRC_IN#
6 OE_0
7 OE_3
8 DIF_0
9 DIF_0#
10 GND
11 VDD
12 DIF_1
13 DIF_1#
14 OE_1
15 OE_2
16 DIF_2
17 DIF_2#
18 GND
19 VDD
20 DIF_3
PWR Power supply, nominal 3.3V
PWR
IN
IN
IN
IN
OUT
OUT
PWR
PWR
Ground pin.
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Active high input for enabling output 0.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling output 3.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Ground pin.
Power supply, nominal 3.3V
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
0.7V differential true clock output
0.7V differential complement clock output
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling output 2.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Ground pin.
Power supply, nominal 3.3V
OUT 0.7V differential true clock output
21 DIF_3#
OUT 0.7V differential complement clock output
22 BYPASS#/PLL
IN
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
23 SCLK
24 SDATA
IN Clock pin of SMBus circuitry, 5V tolerant.
I/O Data pin for SMBus circuitry, 5V tolerant.
IDT^TM/ICS^TM Eight Output Differential Buffer for PCIe Gen 2
3
ICS9DB803DI REV A 06/18/08