ICS9DB401C Datasheet, PDF (5/17 Pages) Integrated Device Technology – Four Output Differential Buffer for PCI Express

ICS9DB401C
Four Output Differential Buffer for PCI Express
Absolute Max
Symbol
VDD_A
VDD_In
V_IL
V_IH
Ts
Tambient
Tcase
ESD prot
Parameter
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
GND-0.5
-65
0
2000
Max
4.6
4.6
V_DD+0.5V
150
70
115
Units
V
V
V
V
°_C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V_IH
3.3 V +/-5%
2
V_IL
3.3 V +/-5%
GND - 0.3
I_IH
V_IN = V_DD
-5
I_IL1
V_IN = 0 V; Inputs with no pull-
up resistors
-5
I_IL2
V_IN = 0 V; Inputs with pull-up
-200
resistors
V_DD + 0.3 V
0.8
V
5
uA
uA
uA
Operating Supply Current ^IDD3.3PLL
I_DD3.3ByPass
Full Active, C_L = Full load;
Powerdown Current
I_DD3.3PD
all diff pairs driven
all differential pairs tri-stated
Input Frequency
F_iPLL
PLL Mode
50
Input Frequency
F_iBypass
Bypass Mode (Revision
B/REV ID = 1H)
0
Input Frequency
F_iBypass
Bypass Mode (Revision
C/REV ID = 2H)
0
Pin Inductance¹
L_pin
Input Capacitance¹
C_IN
Logic Inputs
1.5
C_OUT
Output pin capacitance
PLL Bandwidth when
2.4
PLL Bandwidth
BW
PLL_BW=0
PLL Bandwidth when
0.7
PLL_BW=1
175
200
mA
160
175
mA
40
mA
4
mA
200 MHz
333.33 MHz
400 MHz
7
nH
1
4
pF
1
4
pF
1
3
3.4
MHz
1
1
1.4
MHz
1
Clk Stabilization^1,2
T_STAB
From V_DD Power-Up and after
input clock stabilization or de-
assertion of PD# to 1st clock
0.5
1
ms 1,2
Modulation Frequency fMOD
Triangular Modulation
30
33
kHz
1
Tdrive_SRC_STOP#
DIF output enable after
SRC_Stop# de-assertion
10
15
ns 1,3
Tdrive_PD#
DIF output enable after
PD# de-assertion
300
us 1,3
Tfall
Fall time of PD# and
SRC_STOP#
5
ns
1
Trise
Rise time of PD# and
SRC_STOP#
5
ns
2
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{See timing diagrams for timing requirements.}
3_{Time from deassertion until outputs are >200 mV}
IDT^TM/ICS^TM Four Output Differential Buffer for PCI Express
ICS9DB401C
REV E 03/18/08
5