ICS9DB401C Datasheet, PDF (1/17 Pages) Integrated Device Technology – Four Output Differential Buffer for PCI Express

Four Output Differential Buffer for PCI Express
DATASHEET
ICS9DB401C
Description
The 9DB401C is a DB400 Version 2.0 Yellow Cover part with
PCI Express support. It can be used in PC or embedded
systems to provide outputs that have low cycle-to-cycle jitter
(50ps), low output-to-output skew (100ps), and are PCI Express
gen 1 compliant. The 9DB401C supports a 1 to 4 output
configuration, taking a spread or non spread differential HCSL
input from a CK410(B) main clock such as 954101 and
932S401, or any other differential HCSL pair. 9DB401C can
generate HCSL or LVDS outputs from 50 to 200MHz in PLL
mode or 0 to 400Mhz in bypass mode. There are two de-jittering
modes available selectable through the HIGH_BW# input pin,
high bandwidth mode provides de-jittering for spread inputs and
low bandwidth mode provides extra de-jittering for non-spread
inputs. The SRC_STOP#, PD#, and OE real-time input pins
provide completely programmable power management control.
Output Features
• 4 - 0.7V HCSL or LVDS differential output pairs
• Supports zero delay buffer mode and fanout mode
• Bandwidth programming available
Features/Benefits
• Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
• Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
Key Specifications
• Outputs cycle-cycle jitter: < 50ps
• Outputs skew: < 50ps
• Extended frequency range in bypass mode:
Revision B: up to 333.33MHz
Revision C: up to 400MHz
• Real-time PLL lock detect output pin
• 28-pin SSOP/TSSOP package
• Available in RoHS compliant packaging
Funtional Block Diagram
4
OE(3:0)
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
4
M
U
STOP
X
LOGIC
DIF(3:0))
PD
BYPASS#/PLL
SDATA
SCLK
CONTROL
LOGIC
IREF
Note: Polarities shown for OE_INV = 0.
IDT^TM/ICS^TM Four Output Differential Buffer for PCI Express
1
ICS9DB401C REV E 03/18/08