ICS874001I-05 Datasheet, PDF (5/17 Pages) Integrated Device Technology – PCI EXPRESS™ JITTER ATTENUATOR

ICS874001I-05
PCI EXPRESS™ JITTER ATTENUATOR
TABLE 5. AC CHARACTERISTICS, V_DD = V_DDO = 3.3V ± 0.3V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
tjit(cc)
Output Frequency
Cycle-to-Cycle Jitter,
NOTE 1
T_j
Phase Jitter Peak-to-Peak;
NOTE 2, 4
T_{REFCLK_HF_RMS}
Phase Jitter RMS;
NOTE 3, 4
T_{REFCLK_LF_RMS}
Phase Jitter RMS;
NOTE 3, 4
100MHz output,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
125MHz output,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
250MHz output,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
500MHz, (1.2MHz –21.9MHz),
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
100MHz output,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
125MHz output,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
250MHz output,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
500MHz output,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
100MHz output,
Low Band: 10kHz - 1.5MHz
125MHz output,
Low Band: 10kHz - 1.5MHz
250MHz output,
Low Band: 10kHz - 1.5MHz
500MHz output,
Low Band: 10kHz - 1.5MHz
98
640
MHz
50
ps
16.14
ps
15.64
ps
13.16
ps
12.17
ps
1.4
ps
1.39
ps
1.18
ps
1.11
ps
0.33
ps
0.22
ps
0.22
ps
0.22
ps
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
F_SEL[10] ≠ 11
F_SEL[10] = 11
200
600
ps
48
52
%
42
58
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditons.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Peak-to-peak jitter after system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 10⁶ clock periods. See IDT Application Note,PCI Express Reference Clock Requirements
and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall
composite transfer function.
NOTE 3: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture
and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for
t_{REFCLK_HF_RMS} (High Band) and 3.0ps RMS for t_{REFCLK_LF_RMS} (Low Band). See IDT Application Note,PCI Express Reference Clock
Requirements and also the PCI Express Application section of this datasheet which show each individual transfer function and the
overall composite transfer function.
NOTE 4: Guaranteed only when input clock source is PCI Express and PCI Express Gen 2 compliant.
IDT^™ / ICS^™ PCI EXPRESS JITTER ATTENUATOR
5
ICS874001AGI-05 REV. A APRIL 20, 2009