ICS854S204I Datasheet, PDF (5/19 Pages) Integrated Device Technology – LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIALTO-LVDS, LVPECL FANOUT BUFFER

ICS854S204I
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
TABLE
4I.
LVPECL
DC
CHARACTERISTICS,
V
DD
=
3.3V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions Minimum
V_OH
Output High Voltage; NOTE 1
V_OL
Output Low Voltage; NOTE 1
V_SWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to V_DD - 2V.
SEL_OUT = 1
SEL_OUT = 1
SEL_OUT = 1
V_DD - 1.3
V_DD - 2.0
0.6
Typical
Maximum
V_DD - 0.8
V_DD - 1.6
0.9
Units
V
V
V
TABLE 4J. LVPECL DC CHARACTERISTICS, V_DD = V_TAP = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions Minimum
V_OH
Output High Voltage; NOTE 1
V
Output Low Voltage; NOTE 1
OL
V_SWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to V_DD - 2V.
SEL_OUT = 1
SEL_OUT = 1
SEL_OUT = 1
V_DD - 1.3
V - 2.0
DD
0.6
Typical
Maximum
V_DD - 0.8
V - 1.55
DD
0.9
Units
V
V
V
TABLE
5A.
LVDS
AC
CHARACTERISTICS,
V
DD
=
3.3V
±
5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Output Frequency
3
t_PD
Propagation Delay; NOTE 1
500
tsk(o) Output Skew; NOTE 2, 4
15
tsk(b) Bank Skew; NOTE 3, 4
15
tjit
Buffer Additive Phase Jitter, RMS;
100MHz, Integration Range:
refer to Additive Phase Jitter Section
12kHz – 20MHz
0.15
t /t
RF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
200
49
51
All parameters measured at 550MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured from the output differential cross points.
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Units
GHz
ps
ps
ps
ps
ps
%
TABLE 5B. LVDS AC CHARACTERISTICS, V_DD = V_TAP = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
f_MAX
t
PD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
tsk(b) Bank Skew; NOTE 3, 4
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
49
For NOTES, see Table 5A above.
Typical
0.13
Maximum
3
500
15
15
200
51
Units
GHz
ps
ps
ps
ps
ps
%
IDT^™ / ICS^™ LVDS, LVPECL FANOUT BUFFER
5
ICS854S204BGI REV. A JUNE 4, 2008