ICS854S204I Datasheet, PDF (16/19 Pages) Integrated Device Technology – LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIALTO-LVDS, LVPECL FANOUT BUFFER

ICS854S204I
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
POWER CONSIDERATIONS (LVDS OUTPUTS)
This section provides information on power dissipation and junction temperature for the ICS854S204I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS854S204I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
DD
•
Power = V * I = 3.465V * 120mA = 415.8mW
_MAX
DD_MAX
DD_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS^TM devices is 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T = Ambient Temperature
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ must be used. Assuming no
JA
air flow and a multi-layer board, the appropriate value is 92°C/W per Table 6B below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.416W * 92°C/W = 123.3°C. This is below the limit of 125°C.
TABLE 6B. THERMAL RESISTANCE θ FOR 16-LEAD TSSOP, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
Multi-Layer PCB, JEDEC Standard Test Boards
92°C/W
87.6°C/W
2.5
85.5°C/W
IDT^™ / ICS^™ LVDS, LVPECL FANOUT BUFFER
16
ICS854S204BGI REV. A JUNE 4, 2008