ICS854S204I Datasheet, PDF (11/19 Pages) Integrated Device Technology – LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIALTO-LVDS, LVPECL FANOUT BUFFER

ICS854S204I
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, LVDS, CML, SSTL and
other differential signals. Both V and V must meet the V
SWING
OH
PP
and V_CMR input requirements. Figures 2A to 2F show interface
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with the
vendor of the driver component to confirm the driver termination
requirements.
3.3V
CML
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R1
R2
50
50
3.3V
PCLK
nPCLK _HiPerClockS
PCLK/nPCLK
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A CML DRIVER
3. 3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3. 3V
R3
R4
125
125
3.3V
PCLK
nPCLK _HiPerClockS
I nput
R1
R2
84
84
3.3V
Zo = 50 Ohm
3.3V
R1
PCLK
100
nPCLK
Zo = 50 Ohm
HiPerClockS
CML Built-In Pullup
PCLK/nPCLK
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R3
R4
84
84
C1
C2
R5
100 - 200
R6
100 - 200
R1
R2
125
125
3.3V
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
2.5V
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
2.5V
R3
R4
120
120
3.3V
PCLK
R1
R2
120
120
nPCLK
HiPerClockS
PCLK/nPCLK
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 2F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
IDT^™ / ICS^™ LVDS, LVPECL FANOUT BUFFER
11
ICS854S204BGI REV. A JUNE 4, 2008