9FGP204 Datasheet, PDF (5/18 Pages) Integrated Device Technology – Frequency Timing Generator for Peripherals

9FGP204
Frequency Timing Generator for Peripherals
Truth Table 1: VttPwr_GD/PD# and OE_96
VttPwr_GD/PD#
Pin 40
OE_96
Pin 5
Clocks
0
0
All clocks are powered down
0
1
All clocks are powered down
1
0
All clocks are enabled except DOT96SS
1
1
*All clocks are enabled including DOT96SS
*Assuming DOT96 Output Enable from SMBus Byte2 Bit0 sets to enable (default)
Truth Table 2: VttPwr_GD/PD# and OE_CPU
VttPwr_GD/PD# OE_CPU
Pin 40
Pin 6
Clocks
0
0
All clocks are powered down
0
1
All clocks are powered down
1
0
All clocks are enabled except CPUCLK
1
1
*All clocks are enabled including CPUCLK
*Assuming CPUCLK Output Enable from SMBus Byte2 Bit1 sets to enable (default)
Table 1: CPU Spread and Frequency Selection
CPU
CPU
CPU
CPU
SS_EN
FS2
FS1
FS0
CPU
Byte 0
Byte 0
Byte 0
Byte 0
MHz
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
266.67
0
0
0
1
133.33
0
0
1
0
200.00
0
0
1
1
166.67
0
1
0
0
333.33
0
1
0
1
100.00
0
1
1
0
400.00
0
1
1
1
200.00
1
0
0
0
266.67
1
0
0
1
133.33
1
0
1
0
200.00
1
0
1
1
166.67
1
1
0
0
333.33
1
1
0
1
100.00
1
1
1
0
400.00
1
1
1
1
200.00
Down
Spread %
0%
0%
0%
0%
0%
0%
0%
0%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
IDT^® Frequency Timing Generator for Peripherals
5
1604B—08/29/11