9FGP204 Datasheet, PDF (18/18 Pages) Integrated Device Technology – Frequency Timing Generator for Peripherals

9FGP204
Frequency Timing Generator for Peripherals
Revision History
Rev. Issue Date Who
0.1 6/8/2009 RDW
0.2 11/9/2009 RDW
0.3 1/29/2010 RDW
A 4/7/2010 RDW
B 8/29/2011 RDW
Description
Page #
Initial Release
-
Updated SMBus Byte 4 bits 0, 1 to reserved
1. Updated Series Termination values
2. Added separate Table for RGMII output.
1. Updated Series Termination values and highlighted values are for Zo
= 50 ohms.
2. Raised Idd MAX to 225mA from 200 mA
3. Adding Rise/Fall Matching spec to CPU and DOT96SS Electrical
Tables.
4, 7, 8,
4. Removed All CPU frequencies except 100 from CPU Electrical
9, 10, 11
Table.
5. Updated Min/Max clock periods to reflect new 50 ps cycle to cycle
jitter limit on CPU output.
4. Updated electrical tables with typical values from char report.
1. Removed OE pins for RMII from the block diagram.
3
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Printed in USA
18