844002 Datasheet, PDF (5/16 Pages) Integrated Device Technology – Two LVDS outputs

844002 DATA SHEET
TABLE 5A. AC CHARACTERISTICS, V = V = 3.3V±5%, TA = 0°C TO 70°C
DD
DDO
Symbol Parameter
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
186.67
f
Output Frequency
OUT
F_SEL[1:0] = 01
F_SEL[1:0] = 10
140
93.33
F_SEL[1:0] = 11
46.67
tsk(o) Output Skew; NOTE 1, 2
212.5MHz, (637kHz - 10MHz)
0.65
159.375MHz, (637kHz - 10MHz)
0.61
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
106.25MHz, (637kHz -10MHz)
0.74
53.125MHz, (637kHz - 10MHz)
0.64
187.5MHz, (637kHz - 10MHz)
0.80
t /t
RF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
250
F_SEL[1:0] ≠ ÷3
48
F_SEL[1:0] = ÷3
45
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Maximum
226.66
170
113.33
56.66
15
500
52
55
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
TABLE 5B. AC CHARACTERISTICS, V = V = 2.5V±5%, TA = 0°C TO 70°C
DD
DDO
Symbol Parameter
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
186.67
f
Output Frequency
OUT
F_SEL[1:0] = 01
F_SEL[1:0] = 10
140
93.33
F_SEL[1:0] = 11
46.67
tsk(o) Output Skew; NOTE 1, 2
212.5MHz, (637kHz - 10MHz)
0.65
159.375MHz, (637kHz - 10MHz)
0.61
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
106.25MHz, (637kHz -10MHz)
0.74
53.125MHz, (637kHz - 10MHz)
0.64
187.5MHz, (637kHz - 10MHz)
0.80
t /t
RF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
250
F_SEL[1:0] ≠ ÷3
48
F_SEL[1:0] = ÷3
45
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Maximum
226.66
170
113.33
56.66
15
500
52
55
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
REVISION B 6/9/15
5
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER