844002 Datasheet, PDF (2/16 Pages) Integrated Device Technology – Two LVDS outputs

844002 DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1, 7
nc
Unused
No connect.
2, 20
3, 4
V
DDO
Q0, nQ0
Power
Ouput
Output supply pins.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
5
MR
Input
Pulldown
causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are en-
abled. LVCMOS/LVTTL interface levels.
Selects between the PLL and REF_CLK as input to the dividers. When LOW,
6
nPLL_SEL Input Pulldown selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL
Bypass). LVCMOS/LVTTL interface levels.
8
9, 11
V
DDA
F_SEL0,
F_SEL1
Power
Analog supply pin.
Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
10
12, 13
V
DD
XTAL_OUT,
XTAL_IN
Power
Input
Core supply pins.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
14
REF_CLK Input Pulldown LVCMOS/LVTTL reference clock input.
Selects between crystal or REF_CLK inputs as the the PLL Reference
15 nXTAL_SEL Input Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
16
nc
Unused
No connect.
17
GND
Power
Power supply ground.
18, 19 nQ1, Q1 Output
Differential output pair. LVDS interface levels.
NOTE: refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Pulldown
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
2
FREQUENCY SYNTHESIZER
REVISION B 6/9/15