7028L15PFG8 Datasheet, PDF (5/17 Pages) Integrated Device Technology – True Dual-Ported memory cells which allow simultaneous reads of the same memory location

IDT7028L
High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range⁽²⁾ (VCC = 5.0V ± 10%)
7028L
Symbol
Parameter
Test Conditions
Min.
Max. Unit
|ILI| Input Leakage Current⁽¹⁾
VCC = 5.5V, VIN = 0V to VCC
___
5
µA
|ILO| Output Leakage Current
CE = VIH, VOUT = 0V to VCC
___
5
µA
VOL Output Low Voltage
IOL = 4mA
___
0.4
V
VOH Output High Voltage
IOH = -4mA
2.4
___
V
NOTES:
1. At Vcc < 2.0V, input leakages are undefined.
2. Refer to Chip Enable Truth Table.
4836 tbl 09
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range⁽⁵⁾ (VCC = 5.0V ± 10%)
7028L15
Com'l Only
7028L20
Com'l & Ind
Symbol
Parameter
Test Condition
Version Typ.⁽¹⁾ Max Typ.⁽¹⁾ Max Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
CE = VIL, Outputs Disabled
SEM = VIH
f = fMAX⁽²⁾
COM'L L 220 340 200 300 mA
IND
L
____
____
200 360
ISB1
Standby Current
(Both Ports - TTL Level
Inputs)
CEL = CER = VIH
SEMR = SEML = VIH
f = fMAX⁽²⁾
COM'L L 65 100 50 75 mA
IND
L
____
____
50 120
ISB2
Standby Current
(One Port - TTL Level
Inputs)
CE"A" = VIL and CE"B" = VIH⁽⁴⁾
Active Port Outputs Disabled,
f=fMAX⁽²⁾, SEMR = SEML = VIH
COM'L L 145 225 130 195 mA
IND
L
____
____
130 235
ISB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V, VIN > VCC - 0.2V
or VIN < 0.2V, f = 0⁽³⁾
SEMR = SEML > VCC - 0.2V
COM'L L 0.2 3.0 0.2 3.0 mA
IND
L
____
____
0.2
3.0
ISB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V⁽⁴⁾,
SEMR = SEML > VCC - 0.2V,
VIN > VCC - 0.2V or VIN < 0.2V,
Active Port Outp uts Disabled , f = fMAX⁽²⁾
COM'L L 135 220 120 190 mA
IND
L
____
____
120 230
NOTES:
4836 tbl 10
1. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5. Refer to Chip Enable Truth Table.
6.542