7028L15PFG8 Datasheet, PDF (12/17 Pages) Integrated Device Technology – True Dual-Ported memory cells which allow simultaneous reads of the same memory location

IDT7028L
High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)^(1,3)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
CE"B"
BUSY"B"
tAPS ⁽²⁾
tBAC
tBDC
4836 drw 13
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/S = VIH)⁽¹⁾
ADDR"A"
ADDR"B"
BUSY"B"
ADDRESS "N"
tAPS ⁽²⁾
MATCHING ADDRESS "N"
tBAA
tBDA
4836 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Chip Enable Truth Table.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
Symbol
INTERRUPT TIMING
tAS
Address Set-up Time
tWR
Write Recovery Time
tINS
Interrupt Set Time
tINR
Interrupt Reset Time
Parameter
7028L15
Com'l Only
Min. Max.
0
____
0
____
____
15
____
15
7028L20
Com'l & Ind
Min. Max. Unit
0
____
ns
0
____
ns
____
20
ns
____
20
ns
4836 tbl 15
12