ZSSC1956 Datasheet, PDF (44/215 Pages) Integrated Device Technology – Intelligent Battery Sensor IC

ZSSC1956 Datasheet
3.4.1.3. Register “wdogCfg” – Watchdog Timer Configuration Register
Table 3.12 Register wdogCfg
Name
wdogEna
Address Bits
[0]
wdogPmDis
[1]
wdogIrqFuncEna
[2]
wdogPrescaleCfg
74HEX
[4:3]
Unused
[6:5]
wdogLock
7
Default
1BIN
0BIN
0BIN
01BIN
00BIN
0BIN
Access
RW
RW
RW
RW
RO
RWS
Description
Global enable bit for the watchdog timer.
Note: This bit can only be written when the watchdog is
not locked (wdogLock == 0).
When this bit is set to 1, PMU stops the watchdog during
any power-down state.
Note: This bit can only be written when the watchdog is
not locked (wdogLock == 0).
When this bit is set to 1, the watchdog reloads the preset
value when expiring for the first time and generates an
interrupt instead of a reset. A reset will always be
generated when the watchdog timer expires for the
second time.
Note: This bit can only be written when the watchdog is
not locked (wdogLock == 0) and when the watchdog is
inactive (SSW[7] == 0).
Prescaler configuration:
0 No prescaler active
1 Prescaler of 125 is active
2 Prescaler of 1250 is active
3 Prescaler of 12500 is active
Note: This bit can only be written when the watchdog is
not locked (wdogLock == 0) and when the watchdog is
inactive (SSW[7] == 0).
See Table 3.9 for timing details.
Unused; always write as 0
When this bit is set to 1, all write accesses to the other
bits of this register as well as to the wdogPresetVal
registers are ignored. This bit can only be written to 1
and is only cleared by a power-on reset.
3.5. SBC Sleep Timer
The integrated sleep timer (up counter) is only active when the system is in any low-power state and it is running
with the 125 kHz clock from the low-power oscillator.
The sleep timer consists of three blocks as illustrated in Figure 3.3:
• A fixed prescaler that divides the incoming 125 kHz clock from the low-power oscillator by 12500 to get a
timer resolution of 10 Hz.
• A 16-bit counter that generates an interrupt (signal: stIrq) when the timer reaches the programmed
compare value sleepTCmp (see Table 3.14).
• A 12-bit counter that triggers the PMU (with signal stAdcTrigger) when the timer reaches the programmed
compare value sleepTAdcCmp to power-up the ADC blocks and to perform measurements if one of the
discrete measurement scenarios are configured (see Table 3.13).
© 2016 Integrated Device Technology, Inc.
44
January 29, 2016