ZSSC1956 Datasheet, PDF (163/215 Pages) Integrated Device Technology – Intelligent Battery Sensor IC

ZSSC1956 Datasheet
4.8. SPIB8
4.8.1. Introduction
The SPIB8 module provides a four-wire SPI master module. The three lines SPI_CLK, MOSI and MISO are fully
controlled by hardware while the SSN line must be controlled by software to guarantee the required setup and
hold times. In addition to the AHB-Lite bus interface, this SPI module has an active-high interrupt line and an
additional input to disable the module. This additional input is needed as the rising edge of SSN will execute the
command sent to the SBC. To avoid any problems when the power or system clock is disabled, this input will be
triggered by the PMU and goes to deep sleep (i.e., any power-down mode on the SBC; see section 4.3.3).
Figure 4.7 SPIB8 Block Diagram
AHBlite Bus Interface
SpiCfg
SpiStat
SpiClkCfg
Write SpiData
SpiData
TxBuffer (8 byte)
ShiftReg
RxBit
RxBuffer (8 byte)
Read SpiData
SPI CONTROL LOGIC
TxBit
SPI_CLK
SSN
MOSI
MISO
IRQ
© 2016 Integrated Device Technology, Inc.
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January 29, 2016