ZSSC1956 Datasheet, PDF (178/215 Pages) Integrated Device Technology – Intelligent Battery Sensor IC

ZSSC1956 Datasheet
Note: Another solution for avoiding these conflicts can be that each master performs a write access without any
data to all the other masters to ensure that it is the only master on the bus.
When the ZSSC1956 IBS is accessed as slave, it automatically handles the following conflicts:
• Conflict during transmission of the acknowledge bit following the address byte: this can only occur when
another device has the same slave address or the global call address is used and when this device is not
ready to be accessed and therefore is sending a NACK. It just releases the bus and ignores all actions on
the bus until it detects a RESTART, START, or STOP condition.
• Conflict during transmission of the acknowledge bit following a data byte: this can only occur for a write
transfer when another device has the same slave address or the global call address is used and when
this device is not ready to receive more data and therefore is sending a NACK. It just releases the bus
and ignores all actions on the bus until it detects a RESTART, START, or STOP condition.
• Conflict during transmission of a data byte: this can only occur for a read transfer when another device
has the same slave address and both have sent an ACK in response to the address byte. This conflict
occurs when this device is transmitting a 1 (recessive value) while the other slave is transmitting a 0
(dominant value). This device immediately releases the bus and generates an interrupt with status
S_I2cStConflict (see page 193).
4.10.4. Operating as Slave-Only
When the ZSSC1956 IBS is operating as a pure slave on the I²C™ bus without using the master functionality, the
registers Z2_I2CCLKRATE and Z2_I2CCLKRATE2 are not needed as the clock on the I²C™ bus is always
generated by the master device. The stop and start bits of register Z2_I2CCTRL (see Table 4.54) must always
be set to 0 as the START and STOP conditions are always generated by the master while the multi bit must be
set to 1 to avoid conflicts when enabling the module (see section 4.10.8).
For the ZSSC1956 IBS to be accessible via its own slave address, a non-zero slave address must be prog-
rammed into the addr bit field in the Z2_I2CADDR register (see Table 4.53) and the ack and enI2C bits in the
Z2_I2CCTRL register must be set to 1.
For the ZSSC1956 IBS to be accessible via the global call address (only write access allowed; read access is
rejected), the gc bit in the Z2_I2CADDR register and the ack and enI2C bits must be set to 1. When the slave
module detects a START (or RESTART) condition on the bus, it enables its address checker.
4.10.4.1. Slave Receiver
After the slave detects its own slave address and a write command (see Figure 4.11) and after the slave returns
an ACK, an interrupt with the status S_I2cStRxWrAddr is generated (see page 188) and the module becomes the
slave receiver. It then expands the low phase of the SCL of the acknowledge bit until its interrupt is cleared. As
there is no required content in the data register, software only needs to set the ack bit in the Z2_I2CCTRL
register to the desired value and clear the interrupt (irq bit in the Z2_I2CCTRL register). The programmed
acknowledge bit will be used as the response to the following data byte to be written.
When the ack bit is set to 1, an ACK will be returned, indicating that the module is able to receive further data
bytes. The master can then send a data byte, which will be acknowledged, and the slave generates a new
interrupt after responding with ACK with the status S_I2cStRxWrData (see page 189). Additionally, the low phase
of the acknowledge bit on SCL is expanded until the interrupt is cleared. When the interrupt is active, software
must read the received data byte first before setting the ack bit to the desired value and clearing the interrupt
(irq bit).
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January 29, 2016