8V79S680_17 Datasheet, PDF (43/49 Pages) Integrated Device Technology – JESD204B-Compliant Fanout Buffer and Divider

8V79S680 Datasheet
Termination for QCLK_y, QREF_r LVPECL Outputs (STYLE = 1)
Figure 15 shows an example termination for the QCLK_y, QREF_r LVPECL outputs. In this example, the characteristic transmission line
impedance is 50 The R1 (50) and R2 (50) resistors are matched load terminations. The output is terminated to the termination voltage
V_T. The V_T must be set according to the output amplitude setting defined in Table 7. The termination resistors must be placed close at the line
end.
Figure 15. LVPECL (STYLE = 1) Output Termination
V_T = V_{DD_V} - 1.50V (250 mV Amplitude)
V_T = V_{DD_V} - 1.75V (500 mV Amplitude)
V_T = V_{DD_V} - 2.00V (750mV Amplitude)
V_{DD_V}
V_T
V_T = V_{DD_V} - 2.25V (1000mV Amplitude)
R₁= 50
R₂ = 50
T = 50
LVPECL
Package Exposed Pad Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the
Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package,
as shown in Figure 16. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the
exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB
between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder
joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be
connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and
dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or
testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array
of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended
that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking
inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land.
Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations
are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s
Thermally/Electrically Enhance Lead-frame Base Package, Amkor Technology.
Figure 16. Assembly for Exposed Pad Thermal Release Path - Side View (Drawing not to Scale)
PIN ^SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE
THERMAL VIA
©2017 Integrated Device Technology, Inc.
LAND PATTERN
(GROUND PAD)
43
PIN PAD
June 22, 2017