8V79S680_17 Datasheet, PDF (26/49 Pages) Integrated Device Technology – JESD204B-Compliant Fanout Buffer and Divider

8V79S680 Datasheet
Table 18. SYSREF Control Register Descriptions (Cont.)
Register Description
Bit Field Name
DLC[1:0]
M_DCB[8:0]
P_DCB[6:0]
Field Type
R/W
R/W
R/W
Default
(Binary)
00
Value:
131ps
0 0000
1000
Description
Delay Unit Multiplier:
Effective delay unit for the SYSREF outputs is (1 + DLC[1:0]) ÷ (8 · f_DCO).
DLC[1:0] Effective SYSREF Delay Unit for f_DCO = 983.04MHz
00
131ps
01
262ps
10
393ps
11
524ps
Delay Calibration Block (DCB) DCO feedback divider. Set in conjunction with f_IN and
P_DCB to achieve a DCO frequency of 983.04±20MHz: f_DCO = f_IN ÷ P_DCB · M_DCB.
Value: 8
000 1000 Delay Calibration Block (DCB) DCO input divider. Set in conjunction with f_IN and M_DCB
to achieve DCO frequency of 983.04±20MHz: f_DCO = f_IN ÷ P_DCB · M_DCB. DCO phase
Value: 8 detector frequency should not exceed 200MHz.
©2017 Integrated Device Technology, Inc.
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June 22, 2017