8V79S680_17 Datasheet, PDF (10/49 Pages) Integrated Device Technology – JESD204B-Compliant Fanout Buffer and Divider

8V79S680 Datasheet
Table 6. Recommended Delay Settings for Closest Clock-SYSREF Output Phase Alignment^[a]
Divider Configuration
CLK_y
N = ÷1
0x00
[a] QCLK and QREF outputs are aligned on the incident edge.
REF_r
0x04
Differential Outputs
Table 7. Output Features
Output
Style
Ampl.^[a]
Disable
Power Down
DC Bias
Termination
QCLK_y^[b],
QREF_r^[c]
(Clock)
LVPECL
LVDS
250-1000mV
4 steps
Yes
Yes
50 to V_T[d]
–
100 differential^[e]
[f]
QREF_r
(SYSREF)
LVPECL
LVDS
250-1000mV
4 steps
Yes
Yes
–
Yes^[g]
50 to V_Td
100 differential^{e f}
[a] Amplitudes are measured single-ended. Differential amplitudes supported are 500mV, 1000mV, 1500mV and 2000mV.
[b] y = A0, A1, A2, B0, B1, C0, C1 and D.
[c] r = A0, A1, A2, B0, B1, C0, C1 and D.
[d] V_T = V_{DD_V} – 1.5V (250mV amplitude setting), V_{DD_V} – 1.75V (500mV amplitude setting), V_{DD_V} – 2.0V (750mV amplitude setting),
V_{DD_V} – 2.25V (1000mV amplitude setting).
[e] AC coupling and DC coupling supported.
[f] See Application Information for output termination information.
[g] In JESD204B applications, it is recommended to use QREF_r (SYSREF) outputs configured to LVDS and 500mV amplitude. AC-coupling and
DC-coupling is supported.
©2017 Integrated Device Technology, Inc.
10
June 22, 2017