ICS9E4101 Datasheet, PDF (4/19 Pages) Integrated Device Technology – Programmable Timing Control HubTM for Intel Systems

ICS9E4101
Programmable Timing Control Hub^TM for Intel Systems
General Description
ICS9E4101 follows Intel CK410 Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets. ICS9E4101 is driven with a 14.318MHz crystal. It generates CPU outputs
up to 400MHz. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support.
Block Diagram
X1
XTAL
X2
PLL2
Frequency
Dividers
SCLK
SDATA
Vtt_PWRGD#/PD
FS_A
FS_B
FS_C
ITP_EN
TEST_MODE
TEST_SEL
Control
Logic
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
48MHz, USB
96MHz_DOTT_0
96MHz_DOTC_0
REFOUT
CPUCLKT (2:0)
CPUCLKC (2:0)
SRCCLKT (7:1)
SRCCLKC (7:1)
PCICLK (5:0)
PCICLKF (2:0)
I REF
Power Groups
Pin Number
VDD GND
48
51
1,7
2,6
21,28,34 29
37
38
11
13
42
45
Description
Xtal, Ref
PCICLK outputs
SRCCLK outputs
Master clock, CPU Analog
DOT, USB, PLL_48
CPUCLK clocks
IDT^TM Programmable Timing Control Hub^TM for Intel Systems
4
1408A—01/25/10