ICS9E4101 Datasheet, PDF (2/19 Pages) Integrated Device Technology – Programmable Timing Control HubTM for Intel Systems

ICS9E4101
Programmable Timing Control Hub^TM for Intel Systems
Pin Description
Pin #
1
2
3
4
5
6
7
PIN NAME
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
8
ITP_EN/PCICLK_F0
9
PCICLK_F1
10 PCICLK_F2
11 VDD48
12 USB_48MHz
13 GND
14 DOTT_96MHz
15 DOTC_96MHz
16 FS_B/TEST_MODE
17 Vtt_PwrGd#/PD
18 FS_A_410
19 SRCCLKT1
20 SRCCLKC1
21 VDDSRC
22 SRCCLKT2
23 SRCCLKC2
24 SRCCLKT3
25 SRCCLKC3
26 SRCCLKT4_SATA
27 SRCCLKC4_SATA
28 VDDSRC
PIN TYPE
DESCRIPTION
PWR Power supply for PCI clocks, nominal 3.3V
PWR Ground pin.
OUT PCI clock output.
OUT PCI clock output.
OUT PCI clock output.
PWR Ground pin.
PWR Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
I/O
1 = CPU_ITP pair
0 = SRC pair
OUT Free running PCI clock not affected by PCI_STOP# .
OUT Free running PCI clock not affected by PCI_STOP# .
PWR Power pin for the 48MHz output.3.3V
OUT 48.00MHz USB clock
PWR Ground pin.
OUT True clock of differential pair for 96.00MHz DOT clock.
OUT Complement clock of differential pair for 96.00MHz DOT clock.
3.3V tolerant input for CPU frequency selection. Refer to input
IN
electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE
is a real time input to select between Hi-Z and REF/N divider mode
while in test mode. Refer to Test Clarification Table.
Vtt_PwrGd# is an active low input used to determine when latched
inputs are ready to be sampled. PD is an asynchronous active high
IN
input pin used to put the device into a low power state. The internal
clocks, PLLs and the crystal oscillator are stopped.
3.3V tolerant low threshold input for CPU frequency selection. This
IN pin requires CK410 FSA. Refer to input electrical characteristics for
Vil_FS and Vih_FS threshold values.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
PWR Supply for SRC clocks, 3.3V nominal
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC/SATA pair.
OUT Complement clock of differential SRC/SATA pair.
PWR Supply for SRC clocks, 3.3V nominal
IDT^TM Programmable Timing Control Hub^TM for Intel Systems
2
1408A—01/25/10