ICS9E4101 Datasheet, PDF (17/19 Pages) Integrated Device Technology – Programmable Timing Control HubTM for Intel Systems

ICS9E4101
Programmable Timing Control Hub^TM for Intel Systems
Test Clarification Table
Comments
· FS_C/TEST_SEL is a 3-level latched input.
o Power-up w/ V >= 2.0V to select TEST
o Power-up w/ V < 2.0V to have pin function as
FS_C.
· When pin is FS_C, VIH_FS and VIL_FS levels
apply.
· FS_B/TEST_MODE is a low-threshold input
o VIH_FS and VIL_FS levels apply.
o TEST_MODE is a real time input
· TEST_SEL can be invoked after power up through
SMBus B6b6.
o If TEST is selected by B6b6, only B6b7 controls
TEST_MODE. The FS_B/TEST_Mode pin is not
used.
· Power must be cycled to exit TEST.
HW
FS_C/TEST FS_B/TEST
_SEL
_MODE
HW PIN HW PIN
0
X
1
0
1
0
1
1
SW
TEST
ENTRY REF/N or
BIT
HI-Z
B6b6 B6b7 OUTPUT
0
X NORMAL
X
0
HI-Z
X
1
REF/N
X
0
REF/N
1
1
X
1
REF/N
0
X
1
0
HI-Z
0
X
1
1
REF/N
B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B6b7: 1= REF/N, Default = 0 (HI-Z)
IDT^TM Programmable Timing Control Hub^TM for Intel Systems
17
1408A—01/25/10