ICS841608I Datasheet, PDF (4/17 Pages) Integrated Device Technology – FEMTOCLOCKS CRYSTAL-TO-HCSL CLOCK GENERATOR VCO: 500MHz

ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
TABLE 6.
AC
CHARACTERISTICS,
V
DD
=
3.3V±5%,
TA
=
-40°C
TO
85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
tjit(Ø)
T_j
Output Frequency
RMS Phase Jitter (Random); NOTE 1
Phase Jitter Peak-to-Peak; NOTE 2
T_{REFCLK_HF_RMS}
Phase Jitter RMS; NOTE 3
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 4
VCO/5
VCO/4
100MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
100MHz, (1.2MHz – 50MHz),
10⁶ samples, 25MHz crystal input
125MHz, (1.2MHz – 62.5MHz),
10⁶ samples, 25MHz crystal input
100MHz, 10⁶ samples,
25MHz crystal input
125MHz, 10⁶ samples,
25MHz crystal input
100
125
0.39
0.37
24.36
23.76
2.44
2.37
MHz
MHz
ps
ps
ps
ps
ps
rms
ps
rms
50
ps
tsk(o)
Rise Edge
Rate
Fall Edge Rate
V_RB
V_MAX
V_MIN
V_CROSS
ΔV_CROSS
odc
Output Skew; NOTE 4, 5
Rising Edge Rate; NOTE 6, 7
Falling Edge Rate; NOTE 6, 7
Ringback Voltage; NOTE 6, 8
Absolute Max. Output Voltage; NOTE 9, 10
Absolute Min. Output Voltage; NOTE 9, 11
Absolute Crossing Voltage;
NOTE 9, 12, 13
Total Variation of V over all edges;
Cross
NOTE 9, 12, 14
Output Duty Cycle; NOTE 6, 15
0.6
0.6
-100
-300
250
48
105
4
4
100
1150
550
140
52
ps
V/ns
V/ns
mV
mV
mV
mV
mV
%
T_STABLE
Power-up Stable Clock Output; NOTE 6, 8
500
ps
t_L
PLL Lock Time
NOTE: All specifications are taken at 100MHz and 125MHz.
90
ms
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: RMS jitter after applying system transfer function. See IDT Application Note, PCI Express Reference Clock Requirements. Maximum
limit for PCI Express is 86ps peak-to-peak.
NOTE 3: RMS jitter after applying system transfer function. The pole frequencies for H1 and H2 for PCIe Gen 2 are 8-16MHz and 5-16MHz.
See IDT Application Note, PCI Express Reference Clock Requirements.Maximum limit for PCI Express Generation 2 is 3.1ps rms.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 6: Measurement taken from differential waveform.
NOTE 7: Measurement from -150mV to +150mV on the differential waveform (derived from Qx minus nQx).
The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the
differential zero crossing. See Parameter Measurement Information Section.
NOTE 8: T_STABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the V_RB ±100 differential range. See Parameter Measurement Information Section.
NOTE 9: Measurement taken from single ended waveform.
NOTE 10: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 11: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 12: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section.
NOTE 13: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
Refers to all crossing points for this measurement. See Parameter Measurement Information Section.
NOTE 14: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the V_CROSS
for any particular system. See Parameter Measurement Information Section.
NOTE 15: Input duty cycle must be 50%.
IDT^™ / ICS^™ HCSL CLOCK GENERATOR
4
ICS841608AKI REV. A JUNE 18, 2008