ICS841608I Datasheet, PDF (10/17 Pages) Integrated Device Technology – FEMTOCLOCKS CRYSTAL-TO-HCSL CLOCK GENERATOR VCO: 500MHz

ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
OUTPUTS:
HCSL OUTPUTs
All unused HCSL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
REF_IN INPUT
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_IN to ground.
LVCMOS CONTROL PINS
All control pins have internal pulldowns; additional resistance is
not required but can be added for additional protection. A 1kΩ
resistor can be used.
SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS841608I application
schematic. In this example, the device is operated at V = 3.3V.
DD
The 18pF parallel resonant 25MHz crystal is used. The C1 =
27pF and C2 = 27pF are recommended for frequency accuracy.
For different board layout, the C1 and C2 may be slightly
adjusted for optimizing frequency accuracy. Two examples of
HCSL terminations are shown in this schematic. The decoupling
capacitors should be located as close as possible to the power
pin.
VD D
R1
VDD
10
C3
0. 1u
VD DA
C4
10u
VDD
C1
27pF
X1
25MH z
18pF
C2
27pF
VDD MR/nOE
U1
1
2 ^XTAL_IN
3
4
5
XTAL_OUT
MR/nOE
VDD
6 ^Q0
7 ^nQ0
8
Q1
nQ1
R2
475
24
VDD ₂₃
nQ7
Q7
nQ6
22
21
20
Q6 ₁₉
GND ₁₈
nQ5
Q5
17
VDD
Logic Control Input Examples
Set Logic
VDD _{Input to}
'1'
RU1
1K
To Logic
Input
pins
RD1
Not Install
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD2
1K
ICS841608I
VD D
VDD
(U1:6) VDD (U1:14)
C6
C7
.1uf
.1uf
(U1:24) VDD(U1:31)
C8
.1uf
C5
0.1u
R3 33
R4 33
Zo = 50
TL1
Zo = 50
TL2
R5
R6
50
50
VDD=3.3V
-
+
Recommended for
PCI Express Add-In
Card
HCSL Termination
Zo = 50
TL3
Zo = 50
TL4
R7
R8
50
50
-
+
Recommended for PCI
Express Point-to-Point
Connection
FIGURE 5. ICS841608I SCHEMATIC EXAMPLE
IDT^™ / ICS^™ HCSL CLOCK GENERATOR
10
ICS841608AKI REV. A JUNE 18, 2008