ICS841608I Datasheet, PDF (2/17 Pages) Integrated Device Technology – FEMTOCLOCKS CRYSTAL-TO-HCSL CLOCK GENERATOR VCO: 500MHz

ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1, 2
3
4, 14,
24, 31
XTAL_IN,
XTAL_OUT
MR/nOE
V_DD
Input
Input
Power
Pulldown
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Active HIGH master reset. Active LOW output enable. When logic HIGH, the
internal dividers are reset and the outputs are in high impedance (Hi-Z).
When logic LOW, the internal dividers and the outputs are enabled.
Asynchronous function. LVCMOS/LVTTL interface levels. See Table 3C.
Core supply pins.
5, 6
Q0, nQ0 Output
Differential output pair. HCSL interface levels.
7, 8
Q1, nQ1 Output
Differential output pair. HCSL interface levels.
9, 19, 32 GND
Power
Power supply ground.
10, 11 Q2, nQ2 Output
Differential output pair. HCSL interface levels.
12, 13 Q3, nQ3 Output
Differential output pair. HCSL interface levels.
15, 16 Q4, nQ4 Output
Differential output pair. HCSL interface levels.
17, 18 Q5, nQ5 Output
Differential output pair. HCSL interface levels.
20, 21 Q6, nQ6 Output
Differential output pair. HCSL interface levels.
22, 23 Q7, nQ7 Output
Differential output pair. HCSL interface levels.
25
FSEL
Input Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3A.
HCSL current reference resistor output. An external fixed precision resistor
26
IREF Output
(475Ω) from this pin to ground provides a reference current used for
differential current-mode Qx/nQx clock outputs.
27
BYPASS
Input
Pulldown
Selects PLL operation/PLL bypass operation. Asynchronous function.
LVCMOS/LVTTL interface levels. See Table 3B.
28
V_DDA
Power
Analog supply pin.
29
REF_SEL
Input
Pulldown
Reference select. Selects the input reference source. See Table 3D.
LVCMOS/LVTTL interface levels.
30
REF_IN Input Pulldown LVCMOS/LVTTL PLL reference clock input.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
C_IN
Input Capacitance
R_PULLDOWN Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
TABLE 3A. FSEL FUNCTION TABLE (f_REF = 25MHZ)
Input
Outputs
FSEL
N
Q0:7/nQ0:7
0
5
VCO/5 (100MHz) PCIe (default)
1
4
VCO/4 (125MHz) sRIO
TABLE 3B. BYPASS FUNCTION TABLE
BYPASS
0
Input
PLL Configuration
PLL enabled (default)
1
PLL bypassed (f_OUT = f_REF ÷ N)
TABLE 3C. MR/nOE FUNCTION TABLE
Input
MR/nOE Function
0
Outputs enabled (default)
1
Device reset, outputs disabled (high-impedance)
TABLE 3D. REF_SEL FUNCTION TABLE
Input
REF_SEL
Input Reference
0
XTAL (default)
1
REF_IN
IDT^™ / ICS^™ HCSL CLOCK GENERATOR
2
ICS841608AKI REV. A JUNE 18, 2008