 English |
|
|
|
|
|
|
|
| ICS830S21I Datasheet, PDF (4/11 Pages) Integrated Device Technology – 1-TO-1 2.5V, 3.3V DIFFERENTIAL-TOLVCMOS/LVTTL TRANSLATOR | |||
| |||
| ◁ |
ICS830S21I
1-TO-1, 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
Table 3D. Differential DC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
IIH
IIL
VPP
VCMR
Input High Current
Input Low Current
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
VDD = VIN = 3.465V or 2.625V
VDD = 3.465V or 2.625V, VIN = 0V
-150
0.15
GND + 0.5
VBB
Output Voltage Reference
VDD â 1.4 VDD â 1.3
NOTE 1:VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Maximum
150
1.5
VDD â 0.85
VDD â 1.2
Units
µA
µA
V
V
V
AC Electrical Characteristics
Table 4A. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Parameter Symbol
Test Conditions
fMAX
tPD
tsk(pp)
Output Frequency
Propagation Delay, NOTE 1
Part-to-Part Skew; NOTE 2, 3
tjit
Buffer Additive Phase jitter, RMS;
refer to Additive Phase Jitter Section
350MHz, Integration Range
(12kHz â 20MHz)
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
Æ â¤ 266MHz
Minimum
0.95
Typical
350
Maximum
1.95
525
Units
MHz
ns
ps
0.11
1
ps
85
500
ps
47
53
%
NOTE 1: Measured from the differential input crossing point to the output at VDD/2.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDD/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Table 4B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Parameter Symbol
Test Conditions
fMAX
tPD
tsk(pp)
Output Frequency
Propagation Delay, NOTE 1
Part-to-Part Skew; NOTE 2, 3
tjit
Buffer Additive Phase jitter, RMS;
refer to Additive Phase Jitter Section
350MHz, Integration Range
(12kHz â 20MHz)
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
Æ â¤ 266MHz
Minimum
1
Typical
350
Maximum
2
550
Units
MHz
ns
ps
0.11
1
ps
125
500
ps
47
53
%
NOTE 1: Measured from the differential input crossing point to the output at VDD/2.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDD/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT⢠/ ICS⢠LVCMOS/LVTTL TRANSLATOR
4
ICS830S21AMI REV. A MARCH 21, 2008
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese