8SLVD1204-33 Datasheet, PDF (4/18 Pages) Integrated Device Technology – Two selectable differential clock input pairs

8SLVD1204-33 DATA SHEET
Table 4C. Differential Input DC Characteristics, V_DD = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
PCLK0,
I_IH
Input High
Current
nPCLK1
PCLK1,
nPCLK1
V_DD = V_IN = 3.465V
I_IL
Input Low
Current
PCLK0,
PCLK1
nPCLK0,
nPCLK1
V_DD = 3.465V, V_IN = 0V
V_DD = 3.465V, V_IN = 0V
-10
-150
V_REF
Reference Voltage
for Input Bias
I_REF = ±1mA
V_DD – 1.50
V_PP
V_CMR
Peak-to-Peak Voltage;
NOTE 1
Common Mode Input
Voltage; NOTES 1, 2
f_REF < 1.5 GHz
0.1
f_REF  1.5 GHz
0.2
1.0
NOTE 1: V_IL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined at the crosspoint.
Typical
V_DD – 1.35
Maximum Units
150
µA
µA
µA
V_DD – 1.15
V
1.5
V
1.5
V
V_DD – 0.6
V
Table 4D. LVDS DC Characteristics, V_DD = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
V_OD
V_OD
V_OS
V_OS
Differential Output Voltage
V_OD Magnitude Change
Offset Voltage
V_OS Magnitude Change
247
1.15
Typical
Maximum
454
50
1.45
50
Units
mV
mV
V
mV
2:4, LVDS OUTPUT FANOUT BUFFER
4
REVSION B 03/11/15