8SLVD1204-33 Datasheet, PDF (10/18 Pages) Integrated Device Technology – Two selectable differential clock input pairs

8SLVD1204-33 DATA SHEET
3.3V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS and other differential
signals. Both differential outputs must meet the V_PP and V_CMR input
requirements. Figures 2A to 2E show interface examples for the
PCLK/ nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
PCLK
nPCLK
LVPECL
R1
R2
84Ω
84Ω
Input
Figure 2A. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
Figure 2B. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
3.3V
LVDS
Zo = 50
Zo = 50
3.3V
R1
100
PCLK
nPCLK
LVPECL
Input
Figure 2C. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
Figure 2D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Coupling
Figure 2E. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver with AC Coupling
2:4, LVDS OUTPUT FANOUT BUFFER
10
REVSION B 03/11/15