8SLVD1204-33 Datasheet, PDF (1/18 Pages) Integrated Device Technology – Two selectable differential clock input pairs

2:4, LVDS Output Fanout Buffer
8SLVD1204-33
DATA SHEET
General Description
The 8SLVD1204-33 is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVD1204-33
is characterized to operate from a 3.3V power supply. Guaranteed
output-to-output and part-to-part skew characteristics make the
8SLVD1204-33 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
selectable differential inputs and four low skew outputs are available.
The integrated bias voltage reference enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
• Four low skew, low additive jitter LVDS output pairs
• Two selectable differential clock input pairs
• Differential PCLKx, nPCLKx pairs can accept the following
differential input levels: LVDS, LVPECL
• Maximum input clock frequency: 2GHz
• LVCMOS/LVTTL interface levels for the control input select pin
• Output skew: 20ps (maximum)
• Propagation delay: 310ps (maximum)
• Low additive phase jitter, RMS; f_REF = 156.25MHz, V_PP = 1V,
10kHz - 20MHz: 100fs (maximum)
• Full 3.3V supply voltage
• Lead-free (RoHS 6), 16-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Block Diagram
VDD
PCLK0
nPCLK0
Pulldown
Pullup/Pulldown
GND GND
0
VDD
PCLK1 ^Pulldown
nPCLK1 ^{Pullup/Pulldown}
1
GND GND
VDD
SEL ^{Pullup/Pulldown}
VREF
GND
Reference
Voltage
Generator
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
12 11 10
Q2 ¹³
9
8 V_REF
nQ2 ¹⁴
Q3 ¹⁵
8SLVD1204-33
8XXXXXX
7 nPCLK0
6 PCLK0
nQ3 ¹⁶
5 V_DD
1
2
3
4
16-pin, 3mm x 3mm VFQFN Package
8SLVD1204-33 REVSION B 03/11/15
1
©2015 Integrated Device Technology, Inc.