83052AGILFT Datasheet, PDF (4/17 Pages) Integrated Device Technology – 2 1 single-ended multiplexer

ICS83052I Data Sheet
2:1, SINGLE ENDED MULTIPLEXER
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
V
Input High Voltage
IH
V = 3.3V ± 5%
2
DD
V = 2.5V ± 5%
1.7
DD
V + 0.3 V
DD
V + 0.3 V
DD
V
Input Low Voltage
IL
V = 3.3V ± 5%
-0.3
DD
V = 2.5V ± 5%
-0.3
DD
0.8
V
0.7
V
CLK0, CLK1,
V = 3.3V or 2.5V ± 5%
I
Input High Current ^SEL0
DD
IH
OE
V = 3.3V or 2.5V ± 5%
DD
150
μA
5
μA
CLK0, CLK1,
V = 3.3V or 2.5V ± 5%
-5
μA
I
Input Low Current ^SEL0
DD
IL
OE
V = 3.3V or 2.5V ± 5%
-150
μA
DD
V = 3.3V ± 5%; NOTE 1
2.6
V
DDO
V
Output HighVoltage
V = 2.5V ± 5%; NOTE 1
1.8
V
OH
DDO
V = 1.8V ± 5%; NOTE 1 V - 0.3
V
DDO
DD
V = 3.3V ± 5%; NOTE 1
DDO
0.5
V
V
Output Low Voltage
OL
V = 2.5V ± 5%; NOTE 1
DDO
0.45
V
V = 1.8V ± 5%; NOTE 1
DDO
0.35
V
NOTE 1: Outputs terminated with 50Ω to V /2. See Parameter Measurement section, "Load Test Circuit" diagrams.
DDO
TABLE 5A. AC CHARACTERISTICS, V = V = 3.3V ± 5%, TA = -40°C TO 85°C
DD
DDO
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
f
MAX
tp
LH
tp
HL
tsk(i)
tsk(pp)
tjit
t /t
RF
odc
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Input Skew; NOTE 4
Part-to-Part Skew; NOTE 2, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 3
Output Rise/Fall Time
Output Duty Cycle
155.52MHz,
Integration Range:
12kHz - 20MHz
20% to 80%
250
MHz
2.0
2.4
2.7
ns
2.0
2.5
2.9
ns
36
160
ps
490
ps
0.18
ps
200
700
ps
45
55
%
MUX
MUX Isolation
ISOLATION
45
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from V /2 of the input to V /2 of the output.
DD
DDO
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V /2.
DDO
NOTE 3: Driving only one input clock.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS83052I REVISION B DECEMBER 8, 2011
4
©2011 Integrated Device Technology, Inc.