83052AGILFT Datasheet, PDF (2/17 Pages) Integrated Device Technology – 2 1 single-ended multiplexer

ICS83052I Data Sheet
2:1, SINGLE ENDED MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
V
Power
Output supply pin.
DDO
2
GND
Power
Power supply ground.
3, 6
CLK1, CLK0 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
4
V
Power
Positive supply pin.
DD
Output enable. When LOW, outputs are in HIGH impedance state.
5
OE
Input Pullup
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
Clock select input. See Table 3. Control Input Function Table.
7
SEL0
Input Pulldown
LVCMOS / LVTTL interface levels.
8
Q
Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
C
IN
R
PULLUP
R
PULLDOWN
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
C
PD
(per output)
R
OUT
Output Impedance
Test Conditions
V = 3.465V
DDO
V = 2.625V
DDO
V = 1.89V
DDO
Minimum Typical Maximum Units
4
pF
51
kΩ
51
kΩ
18
pF
19
pF
19
pF
15
Ω
TABLE 3. CONTROL INPUT FUNCTION TABLE
Control Inputs
Input Selected to Q
SEL0
0
CLK0
1
CLK1
ICS83052I REVISION B DECEMBER 8, 2011
2
©2011 Integrated Device Technology, Inc.