ADC1215S Datasheet, PDF (37/40 Pages) NXP Semiconductors – Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs

Integrated Device Technology
ADC1215S series
Single 12-bit ADC; input buffer; CMOS or LVDS DDR digital output
Table 32. LVDS DDR output register 2 (address 0022h) bit description
Default values are highlighted.
Bit
Symbol
Access Value Description
7 to 4 -
0000 not used
3
BIT/BYTE_WISE
R/W
DDR mode for LVDS output
0
bit wise (even data bits output on DAV rising edge / odd data
bits output on DAV falling edge)
1
byte wise (MSB data bits output on DAV rising edge / LSB data
bits output on DAV falling edge)
2 to 0 LVDS_INTTER[2:0] R/W
internal termination for LVDS buffer (DAV and DATA)
000
no internal termination
001
300 
010
180 
011
110 
100
150 
101
100 
110
81 
111
60 
ADC1215S_SER 3
Product data sheet
Rev. 03 — 2 July 2012
© IDT All rights reserved.
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