ADC1215S Datasheet, PDF (12/40 Pages) NXP Semiconductors – Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs

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10.2 Clock and digital output timing
Table 8. Clock and digital output timing characteristics^[1]
Symbol Parameter
Conditions
ADC1410S065
Min Typ Max
Clock timing input: pins CLKP and CLKM
f_clk
t_lat(data)
clock frequency
data latency
time
40
-
65
-
13.5 -
_clk
clock duty cycle DCS_EN = 1
DCS_EN = 0
30
50
70
45
50
55
t_d(s)
sampling delay
time
-
0.8 -
t_wake
wake-up time
-
CMOS Mode timing output: pins D11 to D0 and DAV
76
-
t_PD
propagation
DATA
delay
DAV
13.6 14.9 16.4
-
4.2 -
t_su
set-up time
t_h
hold time
t_r
rise time
DATA
DAV
-
12.5 -
-
3.4 -
[2] _{0.39 -}
2.4
0.26 -
2.4
t_f
fall time
DATA
[2] _{0.19 -}
2.4
ADC1410S080
Min Typ Max
60
-
80
-
13.5 -
30
50
70
45
50
55
-
0.8 -
-
76
-
11.9 12.9 14.4
-
3.6 -
-
9.8 -
-
3.3 -
0.39 -
2.4
0.26 -
2.4
0.19 -
2.4
ADC1410S105
Min Typ Max
75
-
105
-
13.5 -
30
50
70
45
50
55
-
0.8 -
-
76
-
8.0 10.8 12.4
-
3.3 -
-
6.8 -
-
3.1 -
0.39 -
2.4
0.26 -
2.4
0.19 -
2.4
ADC1410S125 Unit
Min Typ Max
100 -
125 MHz
-
13.5 -
clock
cycles
30
50
70 %
45
50
55 %
-
0.8 -
ns
-
76
-
s
8.2 9.7
-
3.4
-
5.6
-
2.8
0.39 -
0.26 -
0.19 -
11.3 ns
-
ns
-
ns
-
ns
2.4 ns
2.4 ns
2.4 ns