ADC1215S Datasheet, PDF (35/40 Pages) NXP Semiconductors – Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs

Integrated Device Technology
ADC1215S series
Single 12-bit ADC; input buffer; CMOS or LVDS DDR digital output
Table 26. Test pattern register 1 (address 0014h) bit description …continued
Default values are highlighted.
Bit
Symbol
Access Value Description
2 to 0 TESTPAT_SEL[2:0]
R/W
digital test pattern select
000
off
001
mid scale
010
FS
011
+FS
100
toggle ‘1111..1111’/’0000..0000’
101
custom test pattern
110
‘1010..1010.’
111
‘010..1010’
Table 27. Test pattern register 2 (address 0015h) bit description
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 0 TESTPAT_USER[11:4] R/W
00000000 custom digital test pattern (bits 11 to 4)
Table 28. Test pattern register 3 (address 0016h) bit description
Default values are highlighted.
Bit
Symbol
Access Value Description
7 to 4 TESTPAT_USER[3:0] R/W
0000
custom digital test pattern (bits 3 to 0)
3 to 0 -
0000
not used
Table 29. Fast OTR register (address 0017h) bit description
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 4 -
0000
not used
3
FASTOTR
R/W
fast Out-of-Range (OTR) detection
0
disabled
1
enabled
2 to 0 FASTOTR_DET[2:0] R/W
set fast OTR detect level
000
20.56 dB
001
16.12 dB
010
11.02 dB
011
7.82 dB
100
5.49 dB
101
3.66 dB
110
2.14 dB
111
0.86 dB
ADC1215S_SER 3
Product data sheet
Rev. 03 — 2 July 2012
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