8T49N287_16 Datasheet, PDF (36/75 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N287 Datasheet
Bit Field Name
DBIT2_0[4:0]
SYN_MODE0
Rsvd
Field Type
R/W
R/W
R/W
Analog PLL0 Control Register Block Field Descriptions
Default Value Description
00000b
Manual Mode Digital Lock Control Setting for VCO2 in Analog PLL0.
Frequency Synthesizer Mode Control for PLL0:
0 = PLL0 jitter attenuates and translates one or more input references
0b
1 = PLL0 synthesizes output frequencies using only the crystal as a reference
Note that the STATE0[1:0] field in the Digital PLL0 Control Register must be set to
Force Freerun state.
-
Reserved. Always write 0 to this bit location. Read values are not defined.
Table 6O. Analog PLL1 Control Register Bit Field Locations and Descriptions
Please contact IDT through one of the methods listed on the last page of this datasheet for details on how to set these fields for a particular
user configuration.
Address (Hex)
00B0
00B1
00B2
00B3
Analog PLL1 Control Register Block Field Locations
D7
D6
D5
D4
D3
D2
D1
CPSET_1[2:0]
RS_1[1:0]
CP_1[1:0]
Rsvd
SYN_MOD
E1
Rsvd
DLCNT_1
Rsvd
VCOMAN_1
DBIT1_1[4:0]
Rsvd
DBIT2_1[4:0]
D0
WPOST_1
DBITM_1
Bit Field Name
CPSET_1[2:0]
RS_1[1:0]
CP_1[1:0]
WPOST_1
DLCNT_1
DBITM_1
Field Type
R/W
R/W
R/W
R/W
R/W
R/W
Analog PLL1 Control Register Block Field Descriptions
Default Value Description
100b
Charge Pump Current Setting for Analog PLL1:
000 = 110µA
001 = 220µA
010 = 330µA
011 = 440µA
100 = 550µA
101 = 660µA
110 = 770µA
111 = 880µA
Internal Loop Filter Series Resistor Setting for Analog PLL1:
00 = 330
01b
01 = 640
10 = 1.2k
11 = 1.79k
Internal Loop Filter Parallel Capacitor Setting for Analog PLL1:
00 = 40pF
01b
01 = 80pF
10 = 140pF
11 = 200pF
Internal Loop Filter 2nd-Pole Setting for Analog PLL1:
1b
0 = Rpost = 497, Cpost = 40pF
1 = Rpost = 1.58k, Cpost = 40pF
Digital Lock Count Setting for Analog PLL1:
Value should be set to 0 (1ppm accuracy) if external capacitor value is >95nF,
1b
otherwise set to 1.
0 = 1ppm accuracy
1 = 16ppm accuracy
Digital Lock Manual Override Setting for Analog PLL1:
0b
0 = Automatic Mode
1 = Manual Mode
©2016 Integrated Device Technology, Inc.
36
Revision 7, October 27, 2016