8T49N287_16 Datasheet, PDF (10/75 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N287 Datasheet
Output Drivers
The Q0 to Q7 clock outputs are provided with register-controlled
output drivers. By selecting the output drive type in the appropriate
register, any of these outputs can support LVCMOS, LVPECL, HCSL
or LVDS logic levels.
The operating voltage ranges of each output is determined by its
independent output power pin (V_CCO) and thus each can have
different output voltage levels. Output voltage levels of 2.5V or 3.3V
are supported for differential operation and LVCMOS operation. In
addition, LVCMOS output operation supports 1.8V V_CCO.
Each output may be enabled or disabled by register bits and/or GPIO
pins configured as Output Enables. The outputs will be enabled if the
register bit and the associated OE pin are both asserted (high). When
disabled an output will be in a high impedance state.
LVCMOS Operation
When a given output is configured to provide LVCMOS levels, then
both the Q and nQ outputs will toggle at the selected output
frequency. All the previously described configuration and control
apply equally to both outputs. Frequency, phase alignment, voltage
levels and enable / disable status apply to both the Q and nQ pins.
When configured as LVCMOS, the Q and nQ outputs can be selected
to be phase-aligned with each other or inverted relative to one
another. Phase-aligned outputs will have increased simultaneous
switching currents which can negatively affect phase noise
performance and power consumption. It is recommended that use of
this selection be kept to a minimum.
Power-Saving Modes
To allow the device to consume the least power possible for a given
application, the following functions are included under register
control:
• PLL1 may be shut down.
• Any unused output, including all output divider and phase
adjustment logic, can be individually powered-off.
• Clock gating on logic that is not being used.
Status / Control Signals and Interrupts
General-Purpose I/Os & Interrupts
The 8T49N287 provides 4 General Purpose Input / Output (GPIO)
pins for miscellaneous status & control functions. Each GPIO may be
configured as an input or an output. Each GPIO may be directly
controlled from register bits or be used as a predefined function as
shown in Table 4. Note that the default state prior to configuration
being loaded from internal OTP or external EEPROM will be to set
each GPIO to function as an Output Enable.
Table 4. GPIO Configuration
Configured as Input
Configured as Output
Fixed Function
Fixed Function
GPIO
Pin
3
2
1
0
Output
Enable
(default)
OE[3]
OE[2]
OE[1]
OE[0]
Output
Enable
OE[7]
OE[6]
OE[5]
OE[4]
Clock
Select
CSEL1
CSEL0
-
-
General
Purpose
GPI[3]
GPI[2]
GPI[1]
GPI[0]
-
LOS[0]
HOLD[0]
LOL[0]
-
LOS[1]
HOLD[1]
LOL[1]
General
Purpose
GPO[3]
GPO[2]
GPO[1]
GPO[0]
If used in the Fixed Function mode of operation, the GPIO bits will
reflect the real-time status of their respective status bits as shown in
Table 4. Note that the LOL signal represents the lock status of the
PLL. It does not account for the process of synchronization of the
output dividers associated with that PLL. The output dividers
programmed to operate from that PLL will automatically go through a
re-synchronization process when the PLL locks or re-locks, or if the
user triggers a re-sync manually via register bit PLLn_SYN. This
synchronization process may result in a period of instability on the
affected outputs for a duration of up to 350ns after the re-lock (LOL
de-asserts) or the PLLn_SYN bit is de-asserted.
Interrupt Functionality
Interrupt functionality includes an interrupt status flag for each of PLL
Loss-of-Lock Status (LOL[1:0]), PLL Holdover Status (HOLD[1:0])
and Input Reference Status (LOS[1:0]) that is set whenever there is
an alarm on any of those signals. The Status Flag will remain set until
the alarm has been cleared and a ‘1’ has been written to the Status
Flag’s register location or if a reset occurs. Each Status Flag will also
have an Interrupt Enable bit that will determine if that Status Flag is
allowed to cause the Interrupt Status to be affected (enabled) or not
(disabled). All Interrupt Enable bits will be in the disabled state after
reset. The Device Interrupt Status flag and nINT output pin are
asserted if any of the enabled Interrupt Status flags are set.
Device Hardware Configuration
The 8T49N287 supports an internal One-Time Programmable (OTP)
memory that can be pre-programmed at the factory with 1 complete
device configuration. If the device is set to read a configuration from
an external, serial EEPROM, then the values read will overwrite the
OTP-defined values.
This configuration can be over-written using the serial interface once
reset is complete. Any configuration written via the programming
interface needs to be re-written after any power cycle or reset. Please
contact IDT if a specific factory-programmed configuration is desired.
©2016 Integrated Device Technology, Inc.
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Revision 7, October 27, 2016