8T49N287_16 Datasheet, PDF (13/75 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N287 Datasheet
I²C Boot-up Initialization Mode
If enabled (via the BOOT_EEP bit in the Startup register), once the
nRST input has been deasserted (high) and its internal power-up
reset sequence has completed, the device will contend for ownership
of the I²C bus to read its initial register settings from a memory
location on the I²C bus. The address of that memory location is kept
in non-volatile memory in the Startup register. During the boot-up
process, the device will not respond to serial control port accesses.
Once the initialization process is complete, the contents of any of the
device’s registers can be altered. It is the responsibility of the user to
make any desired adjustments in initial values directly in the serial
bus memory.
If a NACK is received to any of the read cycles performed by the
device during the initialization process, or if the CRC does not match
the one stored in address E0h of the EEPROM the process will be
aborted and any uninitialized registers will remain with their default
values. The BOOTFAIL bit (021Eh) in the Global Interrupt Status
register will also be set in this event.
If the BOOTFAIL bit is set, then both LOL[n] indicators will be set.
Contents of the EEPROM should be as shown in Table 5.
Table 5. External Serial EEPROM Contents
EEPROM Offset
Contents
(Hex)
D7
D6
D5
D4
D3
D2
D1
00
1
1
1
1
1
1
1
01
1
1
1
1
1
1
1
02
1
1
1
1
1
1
1
03
1
1
1
1
1
1
1
04
1
1
1
1
1
1
1
05
06
07
08 - DF
E0
E1 - FF
1
1
1
1
1
1
1
1
8T49N287 Device I²C Address [6:2]
0
0
0
0
0
0
0
0
Desired contents of Device Registers 08h - DFh
Serial EEPROM CRC
Unused
D0
1
1
1
1
1
Serial EEPROM
Speed Select
0 = 100kHz
1 = 400kHz
1
0
©2016 Integrated Device Technology, Inc.
13
Revision 7, October 27, 2016